Mirror of BoringSSL (grpc依赖)
https://boringssl.googlesource.com/boringssl
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294 lines
9.8 KiB
294 lines
9.8 KiB
#! /usr/bin/env perl |
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# Copyright 2010-2016 The OpenSSL Project Authors. All Rights Reserved. |
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# |
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# Licensed under the OpenSSL license (the "License"). You may not use |
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# this file except in compliance with the License. You can obtain a copy |
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# in the file LICENSE in the source distribution or at |
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# https://www.openssl.org/source/license.html |
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# ==================================================================== |
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# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL |
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# project. The module is, however, dual licensed under OpenSSL and |
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# CRYPTOGAMS licenses depending on where you obtain it. For further |
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# details see http://www.openssl.org/~appro/cryptogams/. |
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# ==================================================================== |
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# This file was adapted to AArch64 from the 32-bit version in ghash-armv4.pl. It |
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# implements the multiplication algorithm described in: |
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# |
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# Câmara, D.; Gouvêa, C. P. L.; López, J. & Dahab, R.: Fast Software |
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# Polynomial Multiplication on ARM Processors using the NEON Engine. |
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# |
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# http://conradoplg.cryptoland.net/files/2010/12/mocrysen13.pdf |
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# |
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# The main distinction to keep in mind between 32-bit NEON and AArch64 SIMD is |
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# AArch64 cannot compute over the upper halves of SIMD registers. In 32-bit |
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# NEON, the low and high halves of the 128-bit register q0 are accessible as |
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# 64-bit registers d0 and d1, respectively. In AArch64, dN is the lower half of |
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# vN. Where the 32-bit version would use the upper half, this file must keep |
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# halves in separate registers. |
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# |
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# The other distinction is in syntax. 32-bit NEON embeds lane information in the |
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# instruction name, while AArch64 uses suffixes on the registers. For instance, |
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# left-shifting 64-bit lanes of a SIMD register in 32-bit would be written: |
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# |
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# vshl.i64 q0, q0, #1 |
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# |
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# in 64-bit, it would be written: |
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# |
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# shl v0.2d, v0.2d, #1 |
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# |
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# See Programmer's Guide for ARMv8-A, section 7 for details. |
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# http://infocenter.arm.com/help/topic/com.arm.doc.den0024a/DEN0024A_v8_architecture_PG.pdf |
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# |
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# Finally, note the 8-bit and 64-bit polynomial multipliers in AArch64 differ |
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# only by suffix. pmull vR.8h, vA.8b, vB.8b multiplies eight 8-bit polynomials |
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# and is always available. pmull vR.1q, vA.1d, vB.1d multiplies a 64-bit |
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# polynomial and is conditioned on the PMULL extension. This file emulates the |
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# latter with the former. |
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use strict; |
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my $flavour = shift; |
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my $output; |
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if ($flavour=~/\w[\w\-]*\.\w+$/) { $output=$flavour; undef $flavour; } |
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else { while (($output=shift) && ($output!~/\w[\w\-]*\.\w+$/)) {} } |
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if ($flavour && $flavour ne "void") { |
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$0 =~ m/(.*[\/\\])[^\/\\]+$/; |
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my $dir = $1; |
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my $xlate; |
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( $xlate="${dir}arm-xlate.pl" and -f $xlate ) or |
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( $xlate="${dir}../../../perlasm/arm-xlate.pl" and -f $xlate) or |
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die "can't locate arm-xlate.pl"; |
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open OUT,"| \"$^X\" \"$xlate\" $flavour \"$output\""; |
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*STDOUT=*OUT; |
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} else { |
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open OUT,">$output"; |
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*STDOUT=*OUT; |
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} |
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my ($Xi, $Htbl, $inp, $len) = map("x$_", (0..3)); # argument block |
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my ($Xl, $Xm, $Xh, $INlo, $INhi) = map("v$_", (0..4)); |
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my ($Hlo, $Hhi, $Hhl) = map("v$_", (5..7)); |
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# d8-d15 are callee-saved, so avoid v8-v15. AArch64 SIMD has plenty of registers |
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# to spare. |
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my ($t0, $t1, $t2, $t3) = map("v$_", (16..19)); |
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my ($t0l_t1l, $t0h_t1h, $t2l_t3l, $t2h_t3h) = map("v$_", (20..23)); |
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my ($k48_k32, $k16_k0) = map("v$_", (24..25)); |
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my $code = ""; |
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# clmul64x64 emits code which emulates pmull $r.1q, $a.1d, $b.1d. $r, $a, and $b |
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# must be distinct from $t* and $k*. $t* are clobbered by the emitted code. |
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sub clmul64x64 { |
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my ($r, $a, $b) = @_; |
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$code .= <<___; |
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ext $t0.8b, $a.8b, $a.8b, #1 // A1 |
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pmull $t0.8h, $t0.8b, $b.8b // F = A1*B |
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ext $r.8b, $b.8b, $b.8b, #1 // B1 |
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pmull $r.8h, $a.8b, $r.8b // E = A*B1 |
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ext $t1.8b, $a.8b, $a.8b, #2 // A2 |
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pmull $t1.8h, $t1.8b, $b.8b // H = A2*B |
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ext $t3.8b, $b.8b, $b.8b, #2 // B2 |
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pmull $t3.8h, $a.8b, $t3.8b // G = A*B2 |
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ext $t2.8b, $a.8b, $a.8b, #3 // A3 |
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eor $t0.16b, $t0.16b, $r.16b // L = E + F |
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pmull $t2.8h, $t2.8b, $b.8b // J = A3*B |
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ext $r.8b, $b.8b, $b.8b, #3 // B3 |
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eor $t1.16b, $t1.16b, $t3.16b // M = G + H |
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pmull $r.8h, $a.8b, $r.8b // I = A*B3 |
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// Here we diverge from the 32-bit version. It computes the following |
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// (instructions reordered for clarity): |
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// |
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// veor \$t0#lo, \$t0#lo, \$t0#hi @ t0 = P0 + P1 (L) |
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// vand \$t0#hi, \$t0#hi, \$k48 |
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// veor \$t0#lo, \$t0#lo, \$t0#hi |
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// |
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// veor \$t1#lo, \$t1#lo, \$t1#hi @ t1 = P2 + P3 (M) |
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// vand \$t1#hi, \$t1#hi, \$k32 |
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// veor \$t1#lo, \$t1#lo, \$t1#hi |
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// |
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// veor \$t2#lo, \$t2#lo, \$t2#hi @ t2 = P4 + P5 (N) |
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// vand \$t2#hi, \$t2#hi, \$k16 |
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// veor \$t2#lo, \$t2#lo, \$t2#hi |
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// |
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// veor \$t3#lo, \$t3#lo, \$t3#hi @ t3 = P6 + P7 (K) |
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// vmov.i64 \$t3#hi, #0 |
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// |
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// \$kN is a mask with the bottom N bits set. AArch64 cannot compute on |
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// upper halves of SIMD registers, so we must split each half into |
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// separate registers. To compensate, we pair computations up and |
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// parallelize. |
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ext $t3.8b, $b.8b, $b.8b, #4 // B4 |
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eor $t2.16b, $t2.16b, $r.16b // N = I + J |
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pmull $t3.8h, $a.8b, $t3.8b // K = A*B4 |
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// This can probably be scheduled more efficiently. For now, we just |
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// pair up independent instructions. |
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zip1 $t0l_t1l.2d, $t0.2d, $t1.2d |
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zip1 $t2l_t3l.2d, $t2.2d, $t3.2d |
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zip2 $t0h_t1h.2d, $t0.2d, $t1.2d |
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zip2 $t2h_t3h.2d, $t2.2d, $t3.2d |
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eor $t0l_t1l.16b, $t0l_t1l.16b, $t0h_t1h.16b |
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eor $t2l_t3l.16b, $t2l_t3l.16b, $t2h_t3h.16b |
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and $t0h_t1h.16b, $t0h_t1h.16b, $k48_k32.16b |
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and $t2h_t3h.16b, $t2h_t3h.16b, $k16_k0.16b |
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eor $t0l_t1l.16b, $t0l_t1l.16b, $t0h_t1h.16b |
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eor $t2l_t3l.16b, $t2l_t3l.16b, $t2h_t3h.16b |
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zip1 $t0.2d, $t0l_t1l.2d, $t0h_t1h.2d |
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zip1 $t2.2d, $t2l_t3l.2d, $t2h_t3h.2d |
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zip2 $t1.2d, $t0l_t1l.2d, $t0h_t1h.2d |
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zip2 $t3.2d, $t2l_t3l.2d, $t2h_t3h.2d |
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ext $t0.16b, $t0.16b, $t0.16b, #15 // t0 = t0 << 8 |
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ext $t1.16b, $t1.16b, $t1.16b, #14 // t1 = t1 << 16 |
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pmull $r.8h, $a.8b, $b.8b // D = A*B |
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ext $t3.16b, $t3.16b, $t3.16b, #12 // t3 = t3 << 32 |
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ext $t2.16b, $t2.16b, $t2.16b, #13 // t2 = t2 << 24 |
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eor $t0.16b, $t0.16b, $t1.16b |
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eor $t2.16b, $t2.16b, $t3.16b |
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eor $r.16b, $r.16b, $t0.16b |
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eor $r.16b, $r.16b, $t2.16b |
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___ |
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} |
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$code .= <<___; |
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#include <openssl/arm_arch.h> |
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.text |
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.global gcm_init_neon |
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.type gcm_init_neon,%function |
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.align 4 |
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gcm_init_neon: |
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AARCH64_VALID_CALL_TARGET |
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// This function is adapted from gcm_init_v8. xC2 is t3. |
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ld1 {$t1.2d}, [x1] // load H |
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movi $t3.16b, #0xe1 |
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shl $t3.2d, $t3.2d, #57 // 0xc2.0 |
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ext $INlo.16b, $t1.16b, $t1.16b, #8 |
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ushr $t2.2d, $t3.2d, #63 |
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dup $t1.4s, $t1.s[1] |
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ext $t0.16b, $t2.16b, $t3.16b, #8 // t0=0xc2....01 |
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ushr $t2.2d, $INlo.2d, #63 |
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sshr $t1.4s, $t1.4s, #31 // broadcast carry bit |
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and $t2.16b, $t2.16b, $t0.16b |
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shl $INlo.2d, $INlo.2d, #1 |
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ext $t2.16b, $t2.16b, $t2.16b, #8 |
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and $t0.16b, $t0.16b, $t1.16b |
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orr $INlo.16b, $INlo.16b, $t2.16b // H<<<=1 |
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eor $Hlo.16b, $INlo.16b, $t0.16b // twisted H |
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st1 {$Hlo.2d}, [x0] // store Htable[0] |
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ret |
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.size gcm_init_neon,.-gcm_init_neon |
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.global gcm_gmult_neon |
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.type gcm_gmult_neon,%function |
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.align 4 |
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gcm_gmult_neon: |
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AARCH64_VALID_CALL_TARGET |
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ld1 {$INlo.16b}, [$Xi] // load Xi |
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ld1 {$Hlo.1d}, [$Htbl], #8 // load twisted H |
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ld1 {$Hhi.1d}, [$Htbl] |
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adrp x9, :pg_hi21:.Lmasks // load constants |
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add x9, x9, :lo12:.Lmasks |
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ld1 {$k48_k32.2d, $k16_k0.2d}, [x9] |
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rev64 $INlo.16b, $INlo.16b // byteswap Xi |
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ext $INlo.16b, $INlo.16b, $INlo.16b, #8 |
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eor $Hhl.8b, $Hlo.8b, $Hhi.8b // Karatsuba pre-processing |
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mov $len, #16 |
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b .Lgmult_neon |
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.size gcm_gmult_neon,.-gcm_gmult_neon |
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.global gcm_ghash_neon |
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.type gcm_ghash_neon,%function |
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.align 4 |
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gcm_ghash_neon: |
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AARCH64_VALID_CALL_TARGET |
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ld1 {$Xl.16b}, [$Xi] // load Xi |
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ld1 {$Hlo.1d}, [$Htbl], #8 // load twisted H |
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ld1 {$Hhi.1d}, [$Htbl] |
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adrp x9, :pg_hi21:.Lmasks // load constants |
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add x9, x9, :lo12:.Lmasks |
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ld1 {$k48_k32.2d, $k16_k0.2d}, [x9] |
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rev64 $Xl.16b, $Xl.16b // byteswap Xi |
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ext $Xl.16b, $Xl.16b, $Xl.16b, #8 |
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eor $Hhl.8b, $Hlo.8b, $Hhi.8b // Karatsuba pre-processing |
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.Loop_neon: |
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ld1 {$INlo.16b}, [$inp], #16 // load inp |
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rev64 $INlo.16b, $INlo.16b // byteswap inp |
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ext $INlo.16b, $INlo.16b, $INlo.16b, #8 |
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eor $INlo.16b, $INlo.16b, $Xl.16b // inp ^= Xi |
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.Lgmult_neon: |
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// Split the input into $INlo and $INhi. (The upper halves are unused, |
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// so it is okay to leave them alone.) |
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ins $INhi.d[0], $INlo.d[1] |
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___ |
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&clmul64x64 ($Xl, $Hlo, $INlo); # H.lo·Xi.lo |
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$code .= <<___; |
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eor $INlo.8b, $INlo.8b, $INhi.8b // Karatsuba pre-processing |
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___ |
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&clmul64x64 ($Xm, $Hhl, $INlo); # (H.lo+H.hi)·(Xi.lo+Xi.hi) |
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&clmul64x64 ($Xh, $Hhi, $INhi); # H.hi·Xi.hi |
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$code .= <<___; |
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ext $t0.16b, $Xl.16b, $Xh.16b, #8 |
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eor $Xm.16b, $Xm.16b, $Xl.16b // Karatsuba post-processing |
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eor $Xm.16b, $Xm.16b, $Xh.16b |
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eor $Xm.16b, $Xm.16b, $t0.16b // Xm overlaps Xh.lo and Xl.hi |
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ins $Xl.d[1], $Xm.d[0] // Xh|Xl - 256-bit result |
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// This is a no-op due to the ins instruction below. |
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// ins $Xh.d[0], $Xm.d[1] |
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// equivalent of reduction_avx from ghash-x86_64.pl |
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shl $t1.2d, $Xl.2d, #57 // 1st phase |
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shl $t2.2d, $Xl.2d, #62 |
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eor $t2.16b, $t2.16b, $t1.16b // |
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shl $t1.2d, $Xl.2d, #63 |
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eor $t2.16b, $t2.16b, $t1.16b // |
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// Note Xm contains {Xl.d[1], Xh.d[0]}. |
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eor $t2.16b, $t2.16b, $Xm.16b |
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ins $Xl.d[1], $t2.d[0] // Xl.d[1] ^= t2.d[0] |
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ins $Xh.d[0], $t2.d[1] // Xh.d[0] ^= t2.d[1] |
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ushr $t2.2d, $Xl.2d, #1 // 2nd phase |
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eor $Xh.16b, $Xh.16b,$Xl.16b |
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eor $Xl.16b, $Xl.16b,$t2.16b // |
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ushr $t2.2d, $t2.2d, #6 |
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ushr $Xl.2d, $Xl.2d, #1 // |
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eor $Xl.16b, $Xl.16b, $Xh.16b // |
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eor $Xl.16b, $Xl.16b, $t2.16b // |
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subs $len, $len, #16 |
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bne .Loop_neon |
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rev64 $Xl.16b, $Xl.16b // byteswap Xi and write |
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ext $Xl.16b, $Xl.16b, $Xl.16b, #8 |
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st1 {$Xl.16b}, [$Xi] |
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ret |
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.size gcm_ghash_neon,.-gcm_ghash_neon |
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.section .rodata |
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.align 4 |
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.Lmasks: |
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.quad 0x0000ffffffffffff // k48 |
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.quad 0x00000000ffffffff // k32 |
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.quad 0x000000000000ffff // k16 |
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.quad 0x0000000000000000 // k0 |
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.asciz "GHASH for ARMv8, derived from ARMv4 version by <appro\@openssl.org>" |
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.align 2 |
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___ |
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foreach (split("\n",$code)) { |
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s/\`([^\`]*)\`/eval $1/geo; |
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print $_,"\n"; |
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} |
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close STDOUT or die "error closing STDOUT: $!"; # enforce flush
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