diff --git a/crypto/cpu_aarch64_apple.c b/crypto/cpu_aarch64_apple.c index de6a8bd0a..c4fb6799a 100644 --- a/crypto/cpu_aarch64_apple.c +++ b/crypto/cpu_aarch64_apple.c @@ -23,8 +23,6 @@ #include -extern uint32_t OPENSSL_armcap_P; - static int has_hw_feature(const char *name) { int value; size_t len = sizeof(value); diff --git a/crypto/cpu_aarch64_freebsd.c b/crypto/cpu_aarch64_freebsd.c index 42d8afa0a..9910261ab 100644 --- a/crypto/cpu_aarch64_freebsd.c +++ b/crypto/cpu_aarch64_freebsd.c @@ -22,7 +22,6 @@ #include -extern uint32_t OPENSSL_armcap_P; // ID_AA64ISAR0_*_VAL are defined starting FreeBSD 13.0. When FreeBSD // 12.x is out of support, these compatibility macros can be removed. diff --git a/crypto/cpu_aarch64_fuchsia.c b/crypto/cpu_aarch64_fuchsia.c index 64bc44895..6b2a8c86d 100644 --- a/crypto/cpu_aarch64_fuchsia.c +++ b/crypto/cpu_aarch64_fuchsia.c @@ -23,7 +23,6 @@ #include -extern uint32_t OPENSSL_armcap_P; void OPENSSL_cpuid_setup(void) { uint32_t hwcap; diff --git a/crypto/cpu_aarch64_linux.c b/crypto/cpu_aarch64_linux.c index 42227115a..7b8aa404b 100644 --- a/crypto/cpu_aarch64_linux.c +++ b/crypto/cpu_aarch64_linux.c @@ -22,8 +22,6 @@ #include -extern uint32_t OPENSSL_armcap_P; - void OPENSSL_cpuid_setup(void) { unsigned long hwcap = getauxval(AT_HWCAP); diff --git a/crypto/cpu_aarch64_openbsd.c b/crypto/cpu_aarch64_openbsd.c index be271f266..34d9304e2 100644 --- a/crypto/cpu_aarch64_openbsd.c +++ b/crypto/cpu_aarch64_openbsd.c @@ -25,7 +25,6 @@ #include "internal.h" -extern uint32_t OPENSSL_armcap_P; void OPENSSL_cpuid_setup(void) { int isar0_mib[] = { CTL_MACHDEP, CPU_ID_AA64ISAR0 }; diff --git a/crypto/cpu_aarch64_sysreg.c b/crypto/cpu_aarch64_sysreg.c index 8f85e8a99..075050133 100644 --- a/crypto/cpu_aarch64_sysreg.c +++ b/crypto/cpu_aarch64_sysreg.c @@ -84,8 +84,6 @@ static uint32_t read_armcap(void) { return armcap; } -extern uint32_t OPENSSL_armcap_P; - void OPENSSL_cpuid_setup(void) { OPENSSL_armcap_P |= read_armcap(); } #endif // OPENSSL_AARCH64 && !OPENSSL_STATIC_ARMCAP && ANDROID_BAREMETAL diff --git a/crypto/cpu_aarch64_win.c b/crypto/cpu_aarch64_win.c index 0630f96ad..8acaf2951 100644 --- a/crypto/cpu_aarch64_win.c +++ b/crypto/cpu_aarch64_win.c @@ -22,7 +22,7 @@ #include -extern uint32_t OPENSSL_armcap_P; + void OPENSSL_cpuid_setup(void) { // We do not need to check for the presence of NEON, as Armv8-A always has it OPENSSL_armcap_P |= ARMV7_NEON; diff --git a/crypto/cpu_arm.c b/crypto/cpu_arm.c index 33259084a..00cf921af 100644 --- a/crypto/cpu_arm.c +++ b/crypto/cpu_arm.c @@ -20,8 +20,6 @@ #include -extern uint32_t OPENSSL_armcap_P; - int CRYPTO_is_NEON_capable_at_runtime(void) { return (OPENSSL_armcap_P & ARMV7_NEON) != 0; } diff --git a/crypto/cpu_arm_freebsd.c b/crypto/cpu_arm_freebsd.c index dcc792055..209a49f08 100644 --- a/crypto/cpu_arm_freebsd.c +++ b/crypto/cpu_arm_freebsd.c @@ -22,7 +22,6 @@ #include #include -extern uint32_t OPENSSL_armcap_P; void OPENSSL_cpuid_setup(void) { unsigned long hwcap = 0, hwcap2 = 0; diff --git a/crypto/cpu_arm_linux.c b/crypto/cpu_arm_linux.c index d13ac215c..e3a237083 100644 --- a/crypto/cpu_arm_linux.c +++ b/crypto/cpu_arm_linux.c @@ -95,8 +95,6 @@ err: return ret; } -extern uint32_t OPENSSL_armcap_P; - static int g_needs_hwcap2_workaround; void OPENSSL_cpuid_setup(void) { diff --git a/crypto/cpu_arm_openbsd.c b/crypto/cpu_arm_openbsd.c index c3463c72e..cd11ceb0f 100644 --- a/crypto/cpu_arm_openbsd.c +++ b/crypto/cpu_arm_openbsd.c @@ -19,7 +19,6 @@ #include -extern uint32_t OPENSSL_armcap_P; void OPENSSL_cpuid_setup(void) { // OpenBSD does not support arm32 machines without NEON diff --git a/crypto/internal.h b/crypto/internal.h index 274a0a828..13d3f6fc9 100644 --- a/crypto/internal.h +++ b/crypto/internal.h @@ -1353,6 +1353,8 @@ OPENSSL_INLINE int CRYPTO_is_ADX_capable(void) { #if defined(OPENSSL_ARM) || defined(OPENSSL_AARCH64) +extern uint32_t OPENSSL_armcap_P; + #if defined(OPENSSL_APPLE) && defined(OPENSSL_ARM) // We do not detect any features at runtime for Apple's 32-bit ARM platforms. On // 64-bit ARM, we detect some post-ARMv8.0 features.