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330 lines
8.9 KiB
330 lines
8.9 KiB
/* |
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* Copyright (c) 2024 Institue of Software Chinese Academy of Sciences (ISCAS). |
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* |
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* This file is part of FFmpeg. |
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* |
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* FFmpeg is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU Lesser General Public |
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* License as published by the Free Software Foundation; either |
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* version 2.1 of the License, or (at your option) any later version. |
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* |
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* FFmpeg is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public |
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* License along with FFmpeg; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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*/ |
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#include "libavutil/riscv/asm.S" |
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.macro vsetvlstatic8 len |
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.if \len <= 4 |
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vsetivli zero, \len, e8, mf4, ta, ma |
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.elseif \len <= 8 |
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vsetivli zero, \len, e8, mf2, ta, ma |
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.elseif \len <= 16 |
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vsetivli zero, \len, e8, m1, ta, ma |
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.elseif \len <= 31 |
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vsetivli zero, \len, e8, m2, ta, ma |
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.endif |
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.endm |
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.macro vsetvlstatic16 len |
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.if \len <= 4 |
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vsetivli zero, \len, e16, mf2, ta, ma |
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.elseif \len <= 8 |
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vsetivli zero, \len, e16, m1, ta, ma |
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.elseif \len <= 16 |
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vsetivli zero, \len, e16, m2, ta, ma |
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.endif |
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.endm |
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.macro vp8_idct_dc_add |
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vlse32.v v0, (a0), a2 |
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lh a5, 0(a1) |
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sh zero, 0(a1) |
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addi a5, a5, 4 |
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srai t1, a5, 3 |
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vsetivli zero, 4*4, e16, m2, ta, ma |
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vzext.vf2 v2, v0 |
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vadd.vx v2, v2, t1 |
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vmax.vx v2, v2, zero |
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vsetvli zero, zero, e8, m1, ta, ma |
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vnclipu.wi v0, v2, 0 |
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vsetivli zero, 4, e8, mf4, ta, ma |
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vsse32.v v0, (a0), a2 |
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.endm |
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.macro vp8_idct_dc_addy |
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vp8_idct_dc_add |
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addi a0, a0, 4 |
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addi a1, a1, 32 |
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.endm |
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func ff_vp8_idct_dc_add_rvv, zve32x |
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vsetivli zero, 4, e8, mf4, ta, ma |
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vp8_idct_dc_add |
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ret |
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endfunc |
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func ff_vp8_idct_dc_add4y_rvv, zve32x |
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vsetivli zero, 4, e8, mf4, ta, ma |
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.rept 3 |
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vp8_idct_dc_addy |
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.endr |
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vp8_idct_dc_add |
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ret |
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endfunc |
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func ff_vp8_idct_dc_add4uv_rvv, zve32x |
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vsetivli zero, 4, e8, mf4, ta, ma |
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vp8_idct_dc_addy |
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vp8_idct_dc_add |
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addi a0, a0, -4 |
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sh2add a0, a2, a0 |
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addi a1, a1, 32 |
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vp8_idct_dc_addy |
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vp8_idct_dc_add |
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ret |
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endfunc |
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.macro bilin_load dst type mn |
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.ifc \type,v |
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add t5, a2, a3 |
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.else |
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addi t5, a2, 1 |
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.endif |
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vle8.v \dst, (a2) |
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vle8.v v2, (t5) |
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vwmulu.vx v28, \dst, t1 |
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vwmaccu.vx v28, \mn, v2 |
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vwaddu.wx v24, v28, t4 |
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vnsra.wi \dst, v24, 3 |
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.endm |
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.macro put_vp8_bilin_h_v len type mn |
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func ff_put_vp8_bilin\len\()_\type\()_rvv, zve32x |
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vsetvlstatic8 \len |
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li t1, 8 |
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li t4, 4 |
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sub t1, t1, \mn |
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1: |
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addi a4, a4, -1 |
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bilin_load v0, \type, \mn |
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vse8.v v0, (a0) |
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add a2, a2, a3 |
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add a0, a0, a1 |
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bnez a4, 1b |
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ret |
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endfunc |
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.endm |
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.macro put_vp8_bilin_hv len |
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func ff_put_vp8_bilin\len\()_hv_rvv, zve32x |
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vsetvlstatic8 \len |
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li t3, 8 |
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sub t1, t3, a5 |
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sub t2, t3, a6 |
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li t4, 4 |
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bilin_load v4, h, a5 |
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add a2, a2, a3 |
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1: |
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addi a4, a4, -1 |
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vwmulu.vx v20, v4, t2 |
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bilin_load v4, h, a5 |
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vwmaccu.vx v20, a6, v4 |
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vwaddu.wx v24, v20, t4 |
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vnsra.wi v0, v24, 3 |
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vse8.v v0, (a0) |
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add a2, a2, a3 |
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add a0, a0, a1 |
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bnez a4, 1b |
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ret |
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endfunc |
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.endm |
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const subpel_filters |
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.byte 0, -6, 123, 12, -1, 0 |
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.byte 2, -11, 108, 36, -8, 1 |
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.byte 0, -9, 93, 50, -6, 0 |
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.byte 3, -16, 77, 77, -16, 3 |
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.byte 0, -6, 50, 93, -9, 0 |
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.byte 1, -8, 36, 108, -11, 2 |
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.byte 0, -1, 12, 123, -6, 0 |
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endconst |
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.macro epel_filter size type regtype |
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lla \regtype\()2, subpel_filters |
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.ifc \type,v |
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addi \regtype\()0, a6, -1 |
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.else |
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addi \regtype\()0, a5, -1 |
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.endif |
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li \regtype\()1, 6 |
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mul \regtype\()0, \regtype\()0, \regtype\()1 |
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add \regtype\()0, \regtype\()0, \regtype\()2 |
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.irp n,1,2,3,4 |
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lb \regtype\n, \n(\regtype\()0) |
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.endr |
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.ifc \size,6 |
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lb \regtype\()5, 5(\regtype\()0) |
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lb \regtype\()0, (\regtype\()0) |
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.endif |
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.endm |
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.macro epel_load dst len size type from_mem regtype |
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.ifc \type,v |
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mv a5, a3 |
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.else |
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li a5, 1 |
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.endif |
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sub t6, a2, a5 |
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add a7, a2, a5 |
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.if \from_mem |
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vle8.v v24, (a2) |
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vle8.v v22, (t6) |
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vle8.v v26, (a7) |
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add a7, a7, a5 |
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vle8.v v28, (a7) |
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vwmulu.vx v16, v24, \regtype\()2 |
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vwmulu.vx v20, v26, \regtype\()3 |
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.ifc \size,6 |
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sub t6, t6, a5 |
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add a7, a7, a5 |
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vle8.v v24, (t6) |
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vle8.v v26, (a7) |
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vwmaccu.vx v16, \regtype\()0, v24 |
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vwmaccu.vx v16, \regtype\()5, v26 |
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.endif |
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vwmaccsu.vx v16, \regtype\()1, v22 |
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vwmaccsu.vx v16, \regtype\()4, v28 |
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.else |
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vwmulu.vx v16, v4, \regtype\()2 |
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vwmulu.vx v20, v6, \regtype\()3 |
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.ifc \size,6 |
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vwmaccu.vx v16, \regtype\()0, v0 |
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vwmaccu.vx v16, \regtype\()5, v10 |
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.endif |
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vwmaccsu.vx v16, \regtype\()1, v2 |
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vwmaccsu.vx v16, \regtype\()4, v8 |
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.endif |
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li t6, 64 |
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vwadd.wx v16, v16, t6 |
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vsetvlstatic16 \len |
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vwadd.vv v24, v16, v20 |
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vnsra.wi v24, v24, 7 |
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vmax.vx v24, v24, zero |
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vsetvlstatic8 \len |
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vnclipu.wi \dst, v24, 0 |
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.endm |
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.macro epel_load_inc dst len size type from_mem regtype |
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epel_load \dst \len \size \type \from_mem \regtype |
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add a2, a2, a3 |
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.endm |
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.macro epel len size type |
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func ff_put_vp8_epel\len\()_\type\()\size\()_rvv, zve32x |
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epel_filter \size \type t |
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vsetvlstatic8 \len |
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1: |
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addi a4, a4, -1 |
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epel_load_inc v30 \len \size \type 1 t |
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vse8.v v30, (a0) |
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add a0, a0, a1 |
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bnez a4, 1b |
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ret |
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endfunc |
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.endm |
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.macro epel_hv len hsize vsize |
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func ff_put_vp8_epel\len\()_h\hsize\()v\vsize\()_rvv, zve32x |
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#if __riscv_xlen == 64 |
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addi sp, sp, -48 |
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.irp n,0,1,2,3,4,5 |
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sd s\n, \n\()<<3(sp) |
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.endr |
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#else |
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addi sp, sp, -24 |
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.irp n,0,1,2,3,4,5 |
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sw s\n, \n\()<<2(sp) |
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.endr |
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#endif |
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sub a2, a2, a3 |
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epel_filter \hsize h t |
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epel_filter \vsize v s |
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vsetvlstatic8 \len |
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.if \hsize == 6 || \vsize == 6 |
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sub a2, a2, a3 |
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epel_load_inc v0 \len \hsize h 1 t |
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.endif |
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epel_load_inc v2 \len \hsize h 1 t |
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epel_load_inc v4 \len \hsize h 1 t |
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epel_load_inc v6 \len \hsize h 1 t |
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epel_load_inc v8 \len \hsize h 1 t |
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.if \hsize == 6 || \vsize == 6 |
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epel_load_inc v10 \len \hsize h 1 t |
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.endif |
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addi a4, a4, -1 |
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1: |
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addi a4, a4, -1 |
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epel_load v30 \len \vsize v 0 s |
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vse8.v v30, (a0) |
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.if \hsize == 6 || \vsize == 6 |
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vmv.v.v v0, v2 |
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.endif |
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vmv.v.v v2, v4 |
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vmv.v.v v4, v6 |
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vmv.v.v v6, v8 |
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.if \hsize == 6 || \vsize == 6 |
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vmv.v.v v8, v10 |
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epel_load_inc v10 \len \hsize h 1 t |
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.else |
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epel_load_inc v8 \len 4 h 1 t |
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.endif |
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add a0, a0, a1 |
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bnez a4, 1b |
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epel_load v30 \len \vsize v 0 s |
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vse8.v v30, (a0) |
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#if __riscv_xlen == 64 |
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.irp n,0,1,2,3,4,5 |
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ld s\n, \n\()<<3(sp) |
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.endr |
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addi sp, sp, 48 |
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#else |
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.irp n,0,1,2,3,4,5 |
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lw s\n, \n\()<<2(sp) |
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.endr |
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addi sp, sp, 24 |
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#endif |
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ret |
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endfunc |
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.endm |
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.irp len,16,8,4 |
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put_vp8_bilin_h_v \len h a5 |
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put_vp8_bilin_h_v \len v a6 |
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put_vp8_bilin_hv \len |
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epel \len 6 h |
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epel \len 4 h |
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epel \len 6 v |
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epel \len 4 v |
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#if __riscv_xlen <= 64 |
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epel_hv \len 6 6 |
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epel_hv \len 4 4 |
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epel_hv \len 6 4 |
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epel_hv \len 4 6 |
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#endif |
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.endr
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