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171 lines
6.4 KiB
171 lines
6.4 KiB
/* |
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* CPU detection code, extracted from mmx.h |
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* (c)1997-99 by H. Dietz and R. Fisher |
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* Converted to C and improved by Fabrice Bellard. |
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* |
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* This file is part of Libav. |
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* |
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* Libav is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU Lesser General Public |
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* License as published by the Free Software Foundation; either |
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* version 2.1 of the License, or (at your option) any later version. |
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* |
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* Libav is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public |
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* License along with Libav; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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*/ |
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#include <stdlib.h> |
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#include <string.h> |
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#include "libavutil/x86_cpu.h" |
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#include "libavutil/cpu.h" |
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/* ebx saving is necessary for PIC. gcc seems unable to see it alone */ |
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#define cpuid(index, eax, ebx, ecx, edx) \ |
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__asm__ volatile ( \ |
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"mov %%"REG_b", %%"REG_S" \n\t" \ |
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"cpuid \n\t" \ |
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"xchg %%"REG_b", %%"REG_S \ |
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: "=a" (eax), "=S" (ebx), "=c" (ecx), "=d" (edx) \ |
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: "0" (index)) |
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#define xgetbv(index, eax, edx) \ |
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__asm__ (".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c" (index)) |
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#define get_eflags(x) \ |
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__asm__ volatile ("pushfl \n" \ |
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"pop %0 \n" \ |
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: "=r"(x)) |
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#define set_eflags(x) \ |
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__asm__ volatile ("push %0 \n" \ |
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"popfl \n" \ |
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:: "r"(x)) |
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/* Function to test if multimedia instructions are supported... */ |
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int ff_get_cpu_flags_x86(void) |
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{ |
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int rval = 0; |
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int eax, ebx, ecx, edx; |
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int max_std_level, max_ext_level, std_caps = 0, ext_caps = 0; |
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int family = 0, model = 0; |
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union { int i[3]; char c[12]; } vendor; |
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#if ARCH_X86_32 |
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x86_reg a, c; |
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/* Check if CPUID is supported by attempting to toggle the ID bit in |
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* the EFLAGS register. */ |
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get_eflags(a); |
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set_eflags(a ^ 0x200000); |
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get_eflags(c); |
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if (a == c) |
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return 0; /* CPUID not supported */ |
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#endif |
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cpuid(0, max_std_level, ebx, ecx, edx); |
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vendor.i[0] = ebx; |
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vendor.i[1] = edx; |
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vendor.i[2] = ecx; |
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if (max_std_level >= 1) { |
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cpuid(1, eax, ebx, ecx, std_caps); |
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family = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff); |
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model = ((eax >> 4) & 0xf) + ((eax >> 12) & 0xf0); |
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if (std_caps & (1 << 15)) |
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rval |= AV_CPU_FLAG_CMOV; |
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if (std_caps & (1 << 23)) |
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rval |= AV_CPU_FLAG_MMX; |
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if (std_caps & (1 << 25)) |
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rval |= AV_CPU_FLAG_MMX2; |
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#if HAVE_SSE |
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if (std_caps & (1 << 25)) |
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rval |= AV_CPU_FLAG_SSE; |
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if (std_caps & (1 << 26)) |
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rval |= AV_CPU_FLAG_SSE2; |
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if (ecx & 1) |
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rval |= AV_CPU_FLAG_SSE3; |
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if (ecx & 0x00000200 ) |
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rval |= AV_CPU_FLAG_SSSE3; |
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if (ecx & 0x00080000 ) |
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rval |= AV_CPU_FLAG_SSE4; |
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if (ecx & 0x00100000 ) |
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rval |= AV_CPU_FLAG_SSE42; |
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#if HAVE_AVX |
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/* Check OXSAVE and AVX bits */ |
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if ((ecx & 0x18000000) == 0x18000000) { |
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/* Check for OS support */ |
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xgetbv(0, eax, edx); |
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if ((eax & 0x6) == 0x6) |
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rval |= AV_CPU_FLAG_AVX; |
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} |
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#endif |
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#endif |
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} |
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cpuid(0x80000000, max_ext_level, ebx, ecx, edx); |
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if (max_ext_level >= 0x80000001) { |
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cpuid(0x80000001, eax, ebx, ecx, ext_caps); |
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if (ext_caps & (1U << 31)) |
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rval |= AV_CPU_FLAG_3DNOW; |
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if (ext_caps & (1 << 30)) |
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rval |= AV_CPU_FLAG_3DNOWEXT; |
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if (ext_caps & (1 << 23)) |
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rval |= AV_CPU_FLAG_MMX; |
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if (ext_caps & (1 << 22)) |
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rval |= AV_CPU_FLAG_MMX2; |
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/* Allow for selectively disabling SSE2 functions on AMD processors |
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with SSE2 support but not SSE4a. This includes Athlon64, some |
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Opteron, and some Sempron processors. MMX, SSE, or 3DNow! are faster |
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than SSE2 often enough to utilize this special-case flag. |
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AV_CPU_FLAG_SSE2 and AV_CPU_FLAG_SSE2SLOW are both set in this case |
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so that SSE2 is used unless explicitly disabled by checking |
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AV_CPU_FLAG_SSE2SLOW. */ |
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if (!strncmp(vendor.c, "AuthenticAMD", 12) && |
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rval & AV_CPU_FLAG_SSE2 && !(ecx & 0x00000040)) { |
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rval |= AV_CPU_FLAG_SSE2SLOW; |
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} |
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/* XOP and FMA4 use the AVX instruction coding scheme, so they can't be |
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* used unless the OS has AVX support. */ |
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if (rval & AV_CPU_FLAG_AVX) { |
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if (ecx & 0x00000800) |
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rval |= AV_CPU_FLAG_XOP; |
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if (ecx & 0x00010000) |
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rval |= AV_CPU_FLAG_FMA4; |
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} |
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} |
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if (!strncmp(vendor.c, "GenuineIntel", 12)) { |
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if (family == 6 && (model == 9 || model == 13 || model == 14)) { |
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/* 6/9 (pentium-m "banias"), 6/13 (pentium-m "dothan"), and |
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* 6/14 (core1 "yonah") theoretically support sse2, but it's |
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* usually slower than mmx, so let's just pretend they don't. |
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* AV_CPU_FLAG_SSE2 is disabled and AV_CPU_FLAG_SSE2SLOW is |
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* enabled so that SSE2 is not used unless explicitly enabled |
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* by checking AV_CPU_FLAG_SSE2SLOW. The same situation |
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* applies for AV_CPU_FLAG_SSE3 and AV_CPU_FLAG_SSE3SLOW. */ |
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if (rval & AV_CPU_FLAG_SSE2) |
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rval ^= AV_CPU_FLAG_SSE2SLOW | AV_CPU_FLAG_SSE2; |
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if (rval & AV_CPU_FLAG_SSE3) |
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rval ^= AV_CPU_FLAG_SSE3SLOW | AV_CPU_FLAG_SSE3; |
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} |
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/* The Atom processor has SSSE3 support, which is useful in many cases, |
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* but sometimes the SSSE3 version is slower than the SSE2 equivalent |
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* on the Atom, but is generally faster on other processors supporting |
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* SSSE3. This flag allows for selectively disabling certain SSSE3 |
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* functions on the Atom. */ |
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if (family == 6 && model == 28) |
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rval |= AV_CPU_FLAG_ATOM; |
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} |
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return rval; |
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}
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