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662 lines
19 KiB
662 lines
19 KiB
/* |
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* Copyright (c) 2014 RISC OS Open Ltd |
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* Author: Ben Avison <bavison@riscosopen.org> |
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* |
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* This file is part of Libav. |
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* |
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* Libav is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU Lesser General Public |
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* License as published by the Free Software Foundation; either |
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* version 2.1 of the License, or (at your option) any later version. |
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* |
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* Libav is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public |
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* License along with Libav; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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*/ |
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#include "libavutil/arm/asm.S" |
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#define MAX_CHANNELS 8 |
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#define MAX_FIR_ORDER 8 |
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#define MAX_IIR_ORDER 4 |
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#define MAX_RATEFACTOR 4 |
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#define MAX_BLOCKSIZE (40 * MAX_RATEFACTOR) |
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PST .req a1 |
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PCO .req a2 |
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AC0 .req a3 |
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AC1 .req a4 |
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CO0 .req v1 |
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CO1 .req v2 |
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CO2 .req v3 |
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CO3 .req v4 |
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ST0 .req v5 |
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ST1 .req v6 |
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ST2 .req sl |
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ST3 .req fp |
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I .req ip |
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PSAMP .req lr |
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.macro branch_pic_label first, remainder:vararg |
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A .word \first - 4 |
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T .hword (\first) / 2 |
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.ifnb \remainder |
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branch_pic_label \remainder |
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.endif |
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.endm |
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// Some macros that do loads/multiplies where the register number is determined |
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// from an assembly-time expression. Boy is GNU assembler's syntax ugly... |
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.macro load group, index, base, offset |
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.altmacro |
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load_ \group, %(\index), \base, \offset |
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.noaltmacro |
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.endm |
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.macro load_ group, index, base, offset |
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ldr \group\index, [\base, #\offset] |
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.endm |
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.macro loadd group, index, base, offset |
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.altmacro |
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loadd_ \group, %(\index), %(\index+1), \base, \offset |
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.noaltmacro |
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.endm |
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.macro loadd_ group, index0, index1, base, offset |
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A .if \offset >= 256 |
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A ldr \group\index0, [\base, #\offset] |
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A ldr \group\index1, [\base, #(\offset) + 4] |
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A .else |
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ldrd \group\index0, \group\index1, [\base, #\offset] |
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A .endif |
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.endm |
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.macro multiply index, accumulate, long |
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.altmacro |
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multiply_ %(\index), \accumulate, \long |
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.noaltmacro |
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.endm |
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.macro multiply_ index, accumulate, long |
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.if \long |
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.if \accumulate |
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smlal AC0, AC1, CO\index, ST\index |
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.else |
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smull AC0, AC1, CO\index, ST\index |
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.endif |
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.else |
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.if \accumulate |
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mla AC0, CO\index, ST\index, AC0 |
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.else |
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mul AC0, CO\index, ST\index |
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.endif |
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.endif |
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.endm |
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// A macro to update the load register number and load offsets |
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.macro inc howmany |
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.set LOAD_REG, (LOAD_REG + \howmany) & 3 |
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.set OFFSET_CO, OFFSET_CO + 4 * \howmany |
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.set OFFSET_ST, OFFSET_ST + 4 * \howmany |
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.if FIR_REMAIN > 0 |
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.set FIR_REMAIN, FIR_REMAIN - \howmany |
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.if FIR_REMAIN == 0 |
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.set OFFSET_CO, 4 * MAX_FIR_ORDER |
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.set OFFSET_ST, 4 * (MAX_BLOCKSIZE + MAX_FIR_ORDER) |
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.endif |
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.elseif IIR_REMAIN > 0 |
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.set IIR_REMAIN, IIR_REMAIN - \howmany |
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.endif |
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.endm |
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// Macro to implement the inner loop for one specific combination of parameters |
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.macro implement_filter mask_minus1, shift_0, shift_8, iir_taps, fir_taps |
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.set TOTAL_TAPS, \iir_taps + \fir_taps |
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// Deal with register allocation... |
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.set DEFINED_SHIFT, 0 |
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.set DEFINED_MASK, 0 |
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.set SHUFFLE_SHIFT, 0 |
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.set SHUFFLE_MASK, 0 |
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.set SPILL_SHIFT, 0 |
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.set SPILL_MASK, 0 |
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.if TOTAL_TAPS == 0 |
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// Little register pressure in this case - just keep MASK where it was |
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.if !\mask_minus1 |
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MASK .req ST1 |
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.set DEFINED_MASK, 1 |
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.endif |
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.else |
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.if \shift_0 |
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.if !\mask_minus1 |
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// AC1 is unused with shift 0 |
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MASK .req AC1 |
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.set DEFINED_MASK, 1 |
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.set SHUFFLE_MASK, 1 |
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.endif |
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.elseif \shift_8 |
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.if !\mask_minus1 |
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.if TOTAL_TAPS <= 4 |
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// All coefficients are preloaded (so pointer not needed) |
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MASK .req PCO |
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.set DEFINED_MASK, 1 |
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.set SHUFFLE_MASK, 1 |
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.else |
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.set SPILL_MASK, 1 |
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.endif |
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.endif |
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.else // shift not 0 or 8 |
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.if TOTAL_TAPS <= 3 |
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// All coefficients are preloaded, and at least one CO register is unused |
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.if \fir_taps & 1 |
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SHIFT .req CO0 |
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.set DEFINED_SHIFT, 1 |
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.set SHUFFLE_SHIFT, 1 |
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.else |
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SHIFT .req CO3 |
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.set DEFINED_SHIFT, 1 |
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.set SHUFFLE_SHIFT, 1 |
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.endif |
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.if !\mask_minus1 |
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MASK .req PCO |
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.set DEFINED_MASK, 1 |
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.set SHUFFLE_MASK, 1 |
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.endif |
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.elseif TOTAL_TAPS == 4 |
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// All coefficients are preloaded |
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SHIFT .req PCO |
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.set DEFINED_SHIFT, 1 |
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.set SHUFFLE_SHIFT, 1 |
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.if !\mask_minus1 |
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.set SPILL_MASK, 1 |
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.endif |
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.else |
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.set SPILL_SHIFT, 1 |
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.if !\mask_minus1 |
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.set SPILL_MASK, 1 |
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.endif |
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.endif |
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.endif |
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.endif |
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.if SPILL_SHIFT |
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SHIFT .req ST0 |
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.set DEFINED_SHIFT, 1 |
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.endif |
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.if SPILL_MASK |
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MASK .req ST1 |
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.set DEFINED_MASK, 1 |
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.endif |
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// Preload coefficients if possible |
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.if TOTAL_TAPS <= 4 |
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.set OFFSET_CO, 0 |
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.if \fir_taps & 1 |
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.set LOAD_REG, 1 |
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.else |
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.set LOAD_REG, 0 |
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.endif |
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.rept \fir_taps |
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load CO, LOAD_REG, PCO, OFFSET_CO |
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.set LOAD_REG, (LOAD_REG + 1) & 3 |
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.set OFFSET_CO, OFFSET_CO + 4 |
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.endr |
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.set OFFSET_CO, 4 * MAX_FIR_ORDER |
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.rept \iir_taps |
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load CO, LOAD_REG, PCO, OFFSET_CO |
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.set LOAD_REG, (LOAD_REG + 1) & 3 |
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.set OFFSET_CO, OFFSET_CO + 4 |
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.endr |
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.endif |
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// Move mask/shift to final positions if necessary |
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// Need to do this after preloading, because in some cases we |
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// reuse the coefficient pointer register |
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.if SHUFFLE_SHIFT |
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mov SHIFT, ST0 |
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.endif |
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.if SHUFFLE_MASK |
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mov MASK, ST1 |
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.endif |
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// Begin loop |
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01: |
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.if TOTAL_TAPS == 0 |
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// Things simplify a lot in this case |
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// In fact this could be pipelined further if it's worth it... |
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ldr ST0, [PSAMP] |
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subs I, I, #1 |
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.if !\mask_minus1 |
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and ST0, ST0, MASK |
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.endif |
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str ST0, [PST, #-4]! |
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str ST0, [PST, #4 * (MAX_BLOCKSIZE + MAX_FIR_ORDER)] |
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str ST0, [PSAMP], #4 * MAX_CHANNELS |
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bne 01b |
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.else |
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.if \fir_taps & 1 |
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.set LOAD_REG, 1 |
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.else |
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.set LOAD_REG, 0 |
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.endif |
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.set LOAD_BANK, 0 |
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.set FIR_REMAIN, \fir_taps |
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.set IIR_REMAIN, \iir_taps |
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.if FIR_REMAIN == 0 // only IIR terms |
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.set OFFSET_CO, 4 * MAX_FIR_ORDER |
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.set OFFSET_ST, 4 * (MAX_BLOCKSIZE + MAX_FIR_ORDER) |
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.else |
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.set OFFSET_CO, 0 |
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.set OFFSET_ST, 0 |
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.endif |
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.set MUL_REG, LOAD_REG |
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.set COUNTER, 0 |
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.rept TOTAL_TAPS + 2 |
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// Do load(s) |
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.if FIR_REMAIN != 0 || IIR_REMAIN != 0 |
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.if COUNTER == 0 |
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.if TOTAL_TAPS > 4 |
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load CO, LOAD_REG, PCO, OFFSET_CO |
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.endif |
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load ST, LOAD_REG, PST, OFFSET_ST |
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inc 1 |
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.elseif COUNTER == 1 && (\fir_taps & 1) == 0 |
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.if TOTAL_TAPS > 4 |
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load CO, LOAD_REG, PCO, OFFSET_CO |
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.endif |
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load ST, LOAD_REG, PST, OFFSET_ST |
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inc 1 |
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.elseif LOAD_BANK == 0 |
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.if TOTAL_TAPS > 4 |
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.if FIR_REMAIN == 0 && IIR_REMAIN == 1 |
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load CO, LOAD_REG, PCO, OFFSET_CO |
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.else |
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loadd CO, LOAD_REG, PCO, OFFSET_CO |
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.endif |
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.endif |
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.set LOAD_BANK, 1 |
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.else |
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.if FIR_REMAIN == 0 && IIR_REMAIN == 1 |
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load ST, LOAD_REG, PST, OFFSET_ST |
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inc 1 |
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.else |
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loadd ST, LOAD_REG, PST, OFFSET_ST |
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inc 2 |
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.endif |
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.set LOAD_BANK, 0 |
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.endif |
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.endif |
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// Do interleaved multiplies, slightly delayed |
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.if COUNTER >= 2 |
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multiply MUL_REG, COUNTER > 2, !\shift_0 |
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.set MUL_REG, (MUL_REG + 1) & 3 |
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.endif |
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.set COUNTER, COUNTER + 1 |
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.endr |
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// Post-process the result of the multiplies |
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.if SPILL_SHIFT |
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ldr SHIFT, [sp, #9*4 + 0*4] |
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.endif |
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.if SPILL_MASK |
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ldr MASK, [sp, #9*4 + 1*4] |
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.endif |
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ldr ST2, [PSAMP] |
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subs I, I, #1 |
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.if \shift_8 |
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mov AC0, AC0, lsr #8 |
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orr AC0, AC0, AC1, lsl #24 |
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.elseif !\shift_0 |
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rsb ST3, SHIFT, #32 |
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mov AC0, AC0, lsr SHIFT |
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A orr AC0, AC0, AC1, lsl ST3 |
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T mov AC1, AC1, lsl ST3 |
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T orr AC0, AC0, AC1 |
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.endif |
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.if \mask_minus1 |
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add ST3, ST2, AC0 |
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.else |
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add ST2, ST2, AC0 |
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and ST3, ST2, MASK |
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sub ST2, ST3, AC0 |
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.endif |
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str ST3, [PST, #-4]! |
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str ST2, [PST, #4 * (MAX_BLOCKSIZE + MAX_FIR_ORDER)] |
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str ST3, [PSAMP], #4 * MAX_CHANNELS |
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bne 01b |
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.endif |
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b 99f |
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.if DEFINED_SHIFT |
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.unreq SHIFT |
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.endif |
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.if DEFINED_MASK |
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.unreq MASK |
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.endif |
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.endm |
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.macro switch_on_fir_taps mask_minus1, shift_0, shift_8, iir_taps |
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A ldr CO0, [pc, a3, lsl #2] // firorder is in range 0-(8-iir_taps) |
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A add pc, pc, CO0 |
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T tbh [pc, a3, lsl #1] |
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0: |
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branch_pic_label (70f - 0b), (71f - 0b), (72f - 0b), (73f - 0b) |
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branch_pic_label (74f - 0b) |
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.if \iir_taps <= 3 |
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branch_pic_label (75f - 0b) |
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.if \iir_taps <= 2 |
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branch_pic_label (76f - 0b) |
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.if \iir_taps <= 1 |
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branch_pic_label (77f - 0b) |
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.if \iir_taps == 0 |
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branch_pic_label (78f - 0b) |
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.endif |
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.endif |
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.endif |
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.endif |
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70: implement_filter \mask_minus1, \shift_0, \shift_8, \iir_taps, 0 |
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71: implement_filter \mask_minus1, \shift_0, \shift_8, \iir_taps, 1 |
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72: implement_filter \mask_minus1, \shift_0, \shift_8, \iir_taps, 2 |
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73: implement_filter \mask_minus1, \shift_0, \shift_8, \iir_taps, 3 |
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74: implement_filter \mask_minus1, \shift_0, \shift_8, \iir_taps, 4 |
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.if \iir_taps <= 3 |
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75: implement_filter \mask_minus1, \shift_0, \shift_8, \iir_taps, 5 |
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.if \iir_taps <= 2 |
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76: implement_filter \mask_minus1, \shift_0, \shift_8, \iir_taps, 6 |
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.if \iir_taps <= 1 |
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77: implement_filter \mask_minus1, \shift_0, \shift_8, \iir_taps, 7 |
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.if \iir_taps == 0 |
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78: implement_filter \mask_minus1, \shift_0, \shift_8, \iir_taps, 8 |
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.endif |
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.endif |
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.endif |
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.endif |
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.endm |
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.macro switch_on_iir_taps mask_minus1, shift_0, shift_8 |
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A ldr CO0, [pc, a4, lsl #2] // irorder is in range 0-4 |
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A add pc, pc, CO0 |
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T tbh [pc, a4, lsl #1] |
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0: |
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branch_pic_label (60f - 0b), (61f - 0b), (62f - 0b), (63f - 0b) |
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branch_pic_label (64f - 0b) |
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60: switch_on_fir_taps \mask_minus1, \shift_0, \shift_8, 0 |
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61: switch_on_fir_taps \mask_minus1, \shift_0, \shift_8, 1 |
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62: switch_on_fir_taps \mask_minus1, \shift_0, \shift_8, 2 |
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63: switch_on_fir_taps \mask_minus1, \shift_0, \shift_8, 3 |
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64: switch_on_fir_taps \mask_minus1, \shift_0, \shift_8, 4 |
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.endm |
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/* void ff_mlp_filter_channel_arm(int32_t *state, const int32_t *coeff, |
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* int firorder, int iirorder, |
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* unsigned int filter_shift, int32_t mask, |
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* int blocksize, int32_t *sample_buffer); |
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*/ |
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function ff_mlp_filter_channel_arm, export=1 |
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push {v1-fp,lr} |
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add v1, sp, #9*4 // point at arguments on stack |
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ldm v1, {ST0,ST1,I,PSAMP} |
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cmp ST1, #-1 |
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bne 30f |
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movs ST2, ST0, lsl #29 // shift is in range 0-15; we want to special-case 0 and 8 |
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bne 20f |
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bcs 10f |
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switch_on_iir_taps 1, 1, 0 |
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10: switch_on_iir_taps 1, 0, 1 |
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20: switch_on_iir_taps 1, 0, 0 |
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30: movs ST2, ST0, lsl #29 // shift is in range 0-15; we want to special-case 0 and 8 |
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bne 50f |
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bcs 40f |
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switch_on_iir_taps 0, 1, 0 |
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40: switch_on_iir_taps 0, 0, 1 |
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50: switch_on_iir_taps 0, 0, 0 |
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99: pop {v1-fp,pc} |
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endfunc |
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.unreq PST |
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.unreq PCO |
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.unreq AC0 |
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.unreq AC1 |
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.unreq CO0 |
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.unreq CO1 |
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.unreq CO2 |
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.unreq CO3 |
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.unreq ST0 |
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.unreq ST1 |
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.unreq ST2 |
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.unreq ST3 |
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.unreq I |
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.unreq PSAMP |
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/********************************************************************/ |
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PSA .req a1 // samples |
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PCO .req a2 // coeffs |
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PBL .req a3 // bypassed_lsbs |
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INDEX .req a4 |
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CO0 .req v1 |
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CO1 .req v2 |
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CO2 .req v3 |
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CO3 .req v4 |
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SA0 .req v5 |
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SA1 .req v6 |
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SA2 .req sl |
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SA3 .req fp |
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AC0 .req ip |
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AC1 .req lr |
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NOISE .req SA0 |
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LSB .req SA1 |
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DCH .req SA2 // dest_ch |
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MASK .req SA3 |
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// INDEX is used as follows: |
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// bits 0..6 index2 (values up to 17, but wider so that we can |
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// add to index field without needing to mask) |
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// bits 7..14 i (values up to 160) |
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// bit 15 underflow detect for i |
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// bits 25..31 (if access_unit_size_pow2 == 128) \ index |
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// bits 26..31 (if access_unit_size_pow2 == 64) / |
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.macro implement_rematrix shift, index_mask, mask_minus1, maxchan |
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.if \maxchan == 1 |
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// We can just leave the coefficients in registers in this case |
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ldrd CO0, CO1, [PCO] |
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.endif |
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1: |
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.if \maxchan == 1 |
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ldrd SA0, SA1, [PSA] |
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smull AC0, AC1, CO0, SA0 |
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.elseif \maxchan == 5 |
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ldr CO0, [PCO, #0] |
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ldr SA0, [PSA, #0] |
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ldr CO1, [PCO, #4] |
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ldr SA1, [PSA, #4] |
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ldrd CO2, CO3, [PCO, #8] |
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smull AC0, AC1, CO0, SA0 |
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ldrd SA2, SA3, [PSA, #8] |
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smlal AC0, AC1, CO1, SA1 |
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ldrd CO0, CO1, [PCO, #16] |
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smlal AC0, AC1, CO2, SA2 |
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ldrd SA0, SA1, [PSA, #16] |
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smlal AC0, AC1, CO3, SA3 |
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smlal AC0, AC1, CO0, SA0 |
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.else // \maxchan == 7 |
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ldr CO2, [PCO, #0] |
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ldr SA2, [PSA, #0] |
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ldr CO3, [PCO, #4] |
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ldr SA3, [PSA, #4] |
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ldrd CO0, CO1, [PCO, #8] |
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smull AC0, AC1, CO2, SA2 |
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ldrd SA0, SA1, [PSA, #8] |
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smlal AC0, AC1, CO3, SA3 |
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ldrd CO2, CO3, [PCO, #16] |
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smlal AC0, AC1, CO0, SA0 |
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ldrd SA2, SA3, [PSA, #16] |
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smlal AC0, AC1, CO1, SA1 |
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ldrd CO0, CO1, [PCO, #24] |
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smlal AC0, AC1, CO2, SA2 |
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ldrd SA0, SA1, [PSA, #24] |
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smlal AC0, AC1, CO3, SA3 |
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smlal AC0, AC1, CO0, SA0 |
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.endif |
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ldm sp, {NOISE, DCH, MASK} |
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smlal AC0, AC1, CO1, SA1 |
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.if \shift != 0 |
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.if \index_mask == 63 |
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add NOISE, NOISE, INDEX, lsr #32-6 |
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ldrb LSB, [PBL], #MAX_CHANNELS |
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ldrsb NOISE, [NOISE] |
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add INDEX, INDEX, INDEX, lsl #32-6 |
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.else // \index_mask == 127 |
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add NOISE, NOISE, INDEX, lsr #32-7 |
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ldrb LSB, [PBL], #MAX_CHANNELS |
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ldrsb NOISE, [NOISE] |
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add INDEX, INDEX, INDEX, lsl #32-7 |
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.endif |
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sub INDEX, INDEX, #1<<7 |
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adds AC0, AC0, NOISE, lsl #\shift + 7 |
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adc AC1, AC1, NOISE, asr #31 |
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.else |
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ldrb LSB, [PBL], #MAX_CHANNELS |
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sub INDEX, INDEX, #1<<7 |
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.endif |
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add PSA, PSA, #MAX_CHANNELS*4 |
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mov AC0, AC0, lsr #14 |
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orr AC0, AC0, AC1, lsl #18 |
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.if !\mask_minus1 |
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and AC0, AC0, MASK |
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.endif |
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add AC0, AC0, LSB |
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tst INDEX, #1<<15 |
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str AC0, [PSA, DCH, lsl #2] // DCH is precompensated for the early increment of PSA |
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beq 1b |
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b 98f |
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.endm |
|
|
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.macro switch_on_maxchan shift, index_mask, mask_minus1 |
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cmp v4, #5 |
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blo 51f |
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beq 50f |
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implement_rematrix \shift, \index_mask, \mask_minus1, 7 |
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50: implement_rematrix \shift, \index_mask, \mask_minus1, 5 |
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51: implement_rematrix \shift, \index_mask, \mask_minus1, 1 |
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.endm |
|
|
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.macro switch_on_mask shift, index_mask |
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cmp sl, #-1 |
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bne 40f |
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switch_on_maxchan \shift, \index_mask, 1 |
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40: switch_on_maxchan \shift, \index_mask, 0 |
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.endm |
|
|
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.macro switch_on_au_size shift |
|
.if \shift == 0 |
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switch_on_mask \shift, undefined |
|
.else |
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teq v6, #64 |
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bne 30f |
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orr INDEX, INDEX, v1, lsl #32-6 |
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switch_on_mask \shift, 63 |
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30: orr INDEX, INDEX, v1, lsl #32-7 |
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switch_on_mask \shift, 127 |
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.endif |
|
.endm |
|
|
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/* void ff_mlp_rematrix_channel_arm(int32_t *samples, |
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* const int32_t *coeffs, |
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* const uint8_t *bypassed_lsbs, |
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* const int8_t *noise_buffer, |
|
* int index, |
|
* unsigned int dest_ch, |
|
* uint16_t blockpos, |
|
* unsigned int maxchan, |
|
* int matrix_noise_shift, |
|
* int access_unit_size_pow2, |
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* int32_t mask); |
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*/ |
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function ff_mlp_rematrix_channel_arm, export=1 |
|
push {v1-fp,lr} |
|
add v1, sp, #9*4 // point at arguments on stack |
|
ldm v1, {v1-sl} |
|
teq v4, #1 |
|
itt ne |
|
teqne v4, #5 |
|
teqne v4, #7 |
|
bne 99f |
|
teq v6, #64 |
|
it ne |
|
teqne v6, #128 |
|
bne 99f |
|
sub v2, v2, #MAX_CHANNELS |
|
push {a4,v2,sl} // initialise NOISE,DCH,MASK; make sp dword-aligned |
|
movs INDEX, v3, lsl #7 |
|
beq 98f // just in case, do nothing if blockpos = 0 |
|
subs INDEX, INDEX, #1<<7 // offset by 1 so we borrow at the right time |
|
adc lr, v1, v1 // calculate index2 (C was set by preceding subs) |
|
orr INDEX, INDEX, lr |
|
// Switch on matrix_noise_shift: values 0 and 1 are |
|
// disproportionately common so do those in a form the branch |
|
// predictor can accelerate. Values can only go up to 15. |
|
cmp v5, #1 |
|
beq 11f |
|
blo 10f |
|
A ldr v5, [pc, v5, lsl #2] |
|
A add pc, pc, v5 |
|
T tbh [pc, v5, lsl #1] |
|
0: |
|
branch_pic_label 0, 0, (12f - 0b), (13f - 0b) |
|
branch_pic_label (14f - 0b), (15f - 0b), (16f - 0b), (17f - 0b) |
|
branch_pic_label (18f - 0b), (19f - 0b), (20f - 0b), (21f - 0b) |
|
branch_pic_label (22f - 0b), (23f - 0b), (24f - 0b), (25f - 0b) |
|
10: switch_on_au_size 0 |
|
11: switch_on_au_size 1 |
|
12: switch_on_au_size 2 |
|
13: switch_on_au_size 3 |
|
14: switch_on_au_size 4 |
|
15: switch_on_au_size 5 |
|
16: switch_on_au_size 6 |
|
17: switch_on_au_size 7 |
|
18: switch_on_au_size 8 |
|
19: switch_on_au_size 9 |
|
20: switch_on_au_size 10 |
|
21: switch_on_au_size 11 |
|
22: switch_on_au_size 12 |
|
23: switch_on_au_size 13 |
|
24: switch_on_au_size 14 |
|
25: switch_on_au_size 15 |
|
|
|
98: add sp, sp, #3*4 |
|
pop {v1-fp,pc} |
|
99: // Can't handle these parameters, drop back to C |
|
pop {v1-fp,lr} |
|
b X(ff_mlp_rematrix_channel) |
|
endfunc |
|
|
|
.unreq PSA |
|
.unreq PCO |
|
.unreq PBL |
|
.unreq INDEX |
|
.unreq CO0 |
|
.unreq CO1 |
|
.unreq CO2 |
|
.unreq CO3 |
|
.unreq SA0 |
|
.unreq SA1 |
|
.unreq SA2 |
|
.unreq SA3 |
|
.unreq AC0 |
|
.unreq AC1 |
|
.unreq NOISE |
|
.unreq LSB |
|
.unreq DCH |
|
.unreq MASK
|
|
|