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N
ffmpeg-0.6.3
n0.10
n0.10.1
n0.10.10
n0.10.11
n0.10.12
n0.10.13
n0.10.14
n0.10.15
n0.10.16
n0.10.2
n0.10.3
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n0.10.6
n0.10.7
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n0.10.9
n0.11
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n0.11.3
n0.11.4
n0.11.5
n0.12-dev
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n0.5.5
n0.5.6
n0.5.7
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n0.5.9
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n0.7.1
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n0.7.17
n0.7.2
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n0.7.6
n0.7.7
n0.7.8
n0.7.9
n0.8
n0.8.1
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n0.8.11
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n0.8.13
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n0.8.3
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n0.8.7
n0.8.8
n0.8.9
n0.9
n0.9.1
n0.9.2
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n1.0
n1.0.1
n1.0.10
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n1.0.6
n1.0.7
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n1.1-dev
n1.1.1
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n1.1.14
n1.1.15
n1.1.16
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n1.2
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n2.5
n2.5-dev
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n2.6-dev
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n2.6.7
n2.6.8
n2.6.9
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n2.8.1
n2.8.10
n2.8.11
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n2.8.17
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n4.2
n4.2-dev
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n4.2.3
n4.2.4
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n4.2.7
n4.2.8
n4.2.9
n4.3
n4.3-dev
n4.3.1
n4.3.2
n4.3.3
n4.3.4
n4.3.5
n4.3.6
n4.3.7
n4.3.8
n4.4
n4.4-dev
n4.4.1
n4.4.2
n4.4.3
n4.4.4
n4.4.5
n4.5-dev
n5.0
n5.0.1
n5.0.2
n5.0.3
n5.1
n5.1-dev
n5.1.1
n5.1.2
n5.1.3
n5.1.4
n5.1.5
n5.1.6
n5.2-dev
n6.0
n6.0.1
n6.1
n6.1-dev
n6.1.1
n6.1.2
n6.2-dev
n7.0
n7.0.1
n7.0.2
n7.1
n7.1-dev
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v0.5
v0.5.1
v0.5.2
v0.5.3
v0.6
v0.6.1
${ noResults }
Måns Rullgård
3c55ce039d
ARMv6 and later support unaligned loads and stores for single word/halfword but not double/multiple. GCC is ignorant of this and will always use bytewise accesses for unaligned data. Casting to an int32_t pointer is dangerous since a load/store double or multiple instruction might be used (this happens with some code in FFmpeg). Implementing the AV_[RW]* macros with inline asm using only supported instructions gives fast and safe unaligned accesses. ARM RVCT does the right thing with generic code. This gives an overall speedup of up to 10%. Originally committed as revision 18601 to svn://svn.ffmpeg.org/ffmpeg/trunk |
16 years ago | |
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.. | ||
bswap.h | ARM: armcc versions of bswap_16/32 | 16 years ago |
intreadwrite.h | ARM asm for AV_RN*() | 16 years ago |
timer.h | ARM: START/STOP_TIMER support for ARMv7 | 16 years ago |