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205 lines
6.2 KiB
205 lines
6.2 KiB
/* |
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* Copyright (c) 2013 RISC OS Open Ltd |
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* Author: Ben Avison <bavison@riscosopen.org> |
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* |
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* This file is part of Libav. |
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* |
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* Libav is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU Lesser General Public |
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* License as published by the Free Software Foundation; either |
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* version 2.1 of the License, or (at your option) any later version. |
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* |
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* Libav is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public |
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* License along with Libav; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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*/ |
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#include "libavutil/arm/asm.S" |
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CONTEXT .req a1 |
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ORIGOUT .req a2 |
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IN .req a3 |
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OUT .req v1 |
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REVTAB .req v2 |
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TCOS .req v3 |
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TSIN .req v4 |
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OLDFPSCR .req v5 |
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J0 .req a2 |
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J1 .req a4 |
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J2 .req ip |
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J3 .req lr |
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.macro prerotation_innerloop |
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.set trig_lo, k |
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.set trig_hi, n4 - k - 2 |
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.set in_lo, trig_lo * 2 |
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.set in_hi, trig_hi * 2 |
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vldr d8, [TCOS, #trig_lo*4] @ s16,s17 |
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vldr d9, [TCOS, #trig_hi*4] @ s18,s19 |
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vldr s0, [IN, #in_hi*4 + 12] |
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vldr s1, [IN, #in_hi*4 + 4] |
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vldr s2, [IN, #in_lo*4 + 12] |
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vldr s3, [IN, #in_lo*4 + 4] |
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vmul.f s8, s0, s16 @ vector operation |
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vldr d10, [TSIN, #trig_lo*4] @ s20,s21 |
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vldr d11, [TSIN, #trig_hi*4] @ s22,s23 |
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vldr s4, [IN, #in_lo*4] |
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vldr s5, [IN, #in_lo*4 + 8] |
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vldr s6, [IN, #in_hi*4] |
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vldr s7, [IN, #in_hi*4 + 8] |
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ldr J0, [REVTAB, #trig_lo*2] |
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vmul.f s12, s0, s20 @ vector operation |
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ldr J2, [REVTAB, #trig_hi*2] |
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mov J1, J0, lsr #16 |
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and J0, J0, #255 @ halfword value will be < n4 |
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vmls.f s8, s4, s20 @ vector operation |
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mov J3, J2, lsr #16 |
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and J2, J2, #255 @ halfword value will be < n4 |
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add J0, OUT, J0, lsl #3 |
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vmla.f s12, s4, s16 @ vector operation |
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add J1, OUT, J1, lsl #3 |
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add J2, OUT, J2, lsl #3 |
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add J3, OUT, J3, lsl #3 |
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vstr s8, [J0] |
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vstr s9, [J1] |
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vstr s10, [J2] |
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vstr s11, [J3] |
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vstr s12, [J0, #4] |
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vstr s13, [J1, #4] |
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vstr s14, [J2, #4] |
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vstr s15, [J3, #4] |
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.set k, k + 2 |
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.endm |
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.macro postrotation_innerloop tail, head |
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.set trig_lo_head, n8 - k - 2 |
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.set trig_hi_head, n8 + k |
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.set out_lo_head, trig_lo_head * 2 |
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.set out_hi_head, trig_hi_head * 2 |
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.set trig_lo_tail, n8 - (k - 2) - 2 |
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.set trig_hi_tail, n8 + (k - 2) |
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.set out_lo_tail, trig_lo_tail * 2 |
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.set out_hi_tail, trig_hi_tail * 2 |
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.if (k & 2) == 0 |
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TCOS_D0_HEAD .req d10 @ s20,s21 |
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TCOS_D1_HEAD .req d11 @ s22,s23 |
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TCOS_S0_TAIL .req s24 |
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.else |
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TCOS_D0_HEAD .req d12 @ s24,s25 |
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TCOS_D1_HEAD .req d13 @ s26,s27 |
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TCOS_S0_TAIL .req s20 |
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.endif |
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.ifnc "\tail","" |
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vmls.f s8, s0, TCOS_S0_TAIL @ vector operation |
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.endif |
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.ifnc "\head","" |
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vldr d8, [TSIN, #trig_lo_head*4] @ s16,s17 |
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vldr d9, [TSIN, #trig_hi_head*4] @ s18,s19 |
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vldr TCOS_D0_HEAD, [TCOS, #trig_lo_head*4] |
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.endif |
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.ifnc "\tail","" |
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vmla.f s12, s4, TCOS_S0_TAIL @ vector operation |
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.endif |
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.ifnc "\head","" |
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vldr s0, [OUT, #out_lo_head*4] |
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vldr s1, [OUT, #out_lo_head*4 + 8] |
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vldr s2, [OUT, #out_hi_head*4] |
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vldr s3, [OUT, #out_hi_head*4 + 8] |
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vldr s4, [OUT, #out_lo_head*4 + 4] |
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vldr s5, [OUT, #out_lo_head*4 + 12] |
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vldr s6, [OUT, #out_hi_head*4 + 4] |
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vldr s7, [OUT, #out_hi_head*4 + 12] |
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.endif |
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.ifnc "\tail","" |
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vstr s8, [OUT, #out_lo_tail*4] |
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vstr s9, [OUT, #out_lo_tail*4 + 8] |
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vstr s10, [OUT, #out_hi_tail*4] |
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vstr s11, [OUT, #out_hi_tail*4 + 8] |
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.endif |
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.ifnc "\head","" |
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vmul.f s8, s4, s16 @ vector operation |
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.endif |
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.ifnc "\tail","" |
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vstr s12, [OUT, #out_hi_tail*4 + 12] |
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vstr s13, [OUT, #out_hi_tail*4 + 4] |
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vstr s14, [OUT, #out_lo_tail*4 + 12] |
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vstr s15, [OUT, #out_lo_tail*4 + 4] |
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.endif |
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.ifnc "\head","" |
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vmul.f s12, s0, s16 @ vector operation |
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vldr TCOS_D1_HEAD, [TCOS, #trig_hi_head*4] |
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.endif |
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.unreq TCOS_D0_HEAD |
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.unreq TCOS_D1_HEAD |
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.unreq TCOS_S0_TAIL |
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.ifnc "\head","" |
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.set k, k + 2 |
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.endif |
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.endm |
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/* void ff_imdct_half_vfp(FFTContext *s, |
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* FFTSample *output, |
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* const FFTSample *input) |
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*/ |
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function ff_imdct_half_vfp, export=1 |
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ldr ip, [CONTEXT, #5*4] @ mdct_bits |
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teq ip, #6 |
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it ne |
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bne X(ff_imdct_half_c) @ only case currently accelerated is the one used by DCA |
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.set n, 1<<6 |
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.set n2, n/2 |
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.set n4, n/4 |
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.set n8, n/8 |
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push {v1-v5,lr} |
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vpush {s16-s27} |
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fmrx OLDFPSCR, FPSCR |
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ldr lr, =0x03030000 @ RunFast mode, short vectors of length 4, stride 1 |
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fmxr FPSCR, lr |
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mov OUT, ORIGOUT |
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ldr REVTAB, [CONTEXT, #2*4] |
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ldr TCOS, [CONTEXT, #6*4] |
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ldr TSIN, [CONTEXT, #7*4] |
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.set k, 0 |
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.rept n8/2 |
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prerotation_innerloop |
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.endr |
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fmxr FPSCR, OLDFPSCR |
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mov a1, OUT |
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bl X(ff_fft16_vfp) |
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ldr lr, =0x03030000 @ RunFast mode, short vectors of length 4, stride 1 |
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fmxr FPSCR, lr |
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.set k, 0 |
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postrotation_innerloop , head |
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.rept n8/2 - 1 |
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postrotation_innerloop tail, head |
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.endr |
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postrotation_innerloop tail |
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fmxr FPSCR, OLDFPSCR |
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vpop {s16-s27} |
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pop {v1-v5,pc} |
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endfunc |
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.unreq CONTEXT |
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.unreq ORIGOUT |
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.unreq IN |
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.unreq OUT |
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.unreq REVTAB |
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.unreq TCOS |
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.unreq TSIN |
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.unreq OLDFPSCR |
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.unreq J0 |
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.unreq J1 |
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.unreq J2 |
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.unreq J3
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