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${ noResults }
6 Commits (c993a91bea88027a329eb7a743f1e8bd6f9c8cfb)
Author | SHA1 | Message | Date |
---|---|---|---|
Rémi Denis-Courmont | 656a9664bf |
checkasm/riscv: preserve T1 whilst calling...
This preserves T1 whilst calling the instrumented function. In a Sci-Fi setting where type-based Control Flow Integrity (CFI) is supported, the calling code (i.e., the `checkasm` test case) will set T1 to the expected value of the landing pad label (LPL) of the instrumented function. The call wrapper will always use LPL zero which is a wild card. We should preserve the value of T1 at least until the indirect call to the instrumented function. Of course this is Sci-Fi, because: 1) there is no hardware (or even QEMU) support yet, 2) all our assembler functions currently use LPL zero anyway. This uses T3 rather than T2 because indirect branches with T2 is reserved for notionally direct calls made with an indirect call instruction (e.g. due to GOT indirection), and are exempted from forward-edge CFI checks. |
5 months ago |
Rémi Denis-Courmont | 8030876d1c |
checkasm/riscv: align the landing pads
|
5 months ago |
Rémi Denis-Courmont | 7dde8be29f |
checkasm/riscv: add forward-edge CFI landing pads
|
5 months ago |
Martin Storsjö | 65739691b9 |
checkasm: Generalize crash handling
This replaces the riscv specific handling from
|
12 months ago |
Rémi Denis-Courmont | 7212466e73 |
checkasm/riscv: report an error upon SIGILL
Terminating the whole checkasm process is not very helpful. This will report if an illegal instruction occurs while executing a tested function. This is a common occurrence whilst developping RISC-V assembler, due to the compatibility between vector configuration and instruction done at run-time. |
1 year ago |
Rémi Denis-Courmont | c962c78901 |
checkasm: RISC-V 64-bit assembler test harness
|
2 years ago |