FFmpeg

Commit Graph

Author	SHA1	Message	Date
Rémi Denis-Courmont	c1bb19e263	lavu/fixeddsp: RISC-V V butterflies_fixed	2 years ago
Rémi Denis-Courmont	cd77662953	lavu/floatdsp: RISC-V V scalarproduct_float	2 years ago
Rémi Denis-Courmont	b493370662	lavu/floatdsp: RISC-V V vector_fmul_window	2 years ago
Rémi Denis-Courmont	9aeb6aca3a	lavu/floatdsp: RISC-V V vector_fmul_reverse	2 years ago
Rémi Denis-Courmont	47ce9735cc	lavu/floatdsp: RISC-V V butterflies_float	2 years ago
Rémi Denis-Courmont	f4ea45040f	lavu/floatdsp: RISC-V V vector_fmul_add	2 years ago
Rémi Denis-Courmont	d120ab5b91	lavu/floatdsp: RISC-V V vector_dmac_scalar	2 years ago
Rémi Denis-Courmont	c3db27ba95	lavu/floatdsp: RISC-V V vector_fmac_scalar	2 years ago
Rémi Denis-Courmont	da169a210d	lavu/floatdsp: RISC-V V vector_dmul	2 years ago
Rémi Denis-Courmont	7058af9969	lavu/floatdsp: RISC-V V vector_fmul	2 years ago
Rémi Denis-Courmont	89b7ec65a8	lavu/floatdsp: RISC-V V vector_dmul_scalar	2 years ago
Rémi Denis-Courmont	a6c10d05fe	lavu/floatdsp: RISC-V V vector_fmul_scalar This is based on existing code from the VLC git tree with two minor changes to account for the different function prototypes.	2 years ago
Rémi Denis-Courmont	39357cad37	lavu/riscv: fallback macros for SH{1, 2, 3}ADD Those mnemonics require the very latest binutils release at the time of writing. These macros provide seamless backward compatibility.	2 years ago
Rémi Denis-Courmont	0c0a3deb18	lavu/cpu: CPU flags for the RISC-V Vector extension RVV defines a total of 12 different extensions, including: - 5 different instruction subsets: - Zve32x: 8-, 16- and 32-bit integers, - Zve32f: Zve32x plus single precision floats, - Zve64x: Zve32x plus 64-bit integers, - Zve64f: Zve32f plus Zve64x, - Zve64d: Zve64f plus double precision floats. - 6 different vector lengths: - Zvl32b (embedded only), - Zvl64b (embedded only), - Zvl128b, - Zvl256b, - Zvl512b, - Zvl1024b, - and the V extension proper: equivalent to Zve64f and Zvl128b. In total, there are 6 different possible sets of supported instructions (including the empty set), but for convenience we allocate one bit for each type sets: up-to-32-bit ints (RVV_I32), floats (RVV_F32), 64-bit ints (RVV_I64) and doubles (RVV_F64). Whence the vector size is needed, it can be retrieved by reading the unprivileged read-only vlenb CSR. This should probably be a separate helper macro if needed at a later point.	2 years ago
Rémi Denis-Courmont	746f1ff36a	lavu/riscv: initial common header for assembler macros	2 years ago
Rémi Denis-Courmont	b95e2fbd85	lavu/cpu: detect RISC-V base extensions This introduces compile-time and run-time CPU detection on RISC-V. In practice, I doubt that FFmpeg will ever see a RISC-V CPU without all of I, F and D extensions, and if it does, it probably won't have run-time detection. So the flags are essentially always set. But as things stand, checkasm wants them that way. Compare the ARMV8 flag on AArch64. We are nowhere near running short on CPU flag bits.	2 years ago
Rémi Denis-Courmont	6df3ad9687	lavu/riscv: fix off-by-one in bit-magnitude clip	2 years ago
Rémi Denis-Courmont	a5ce44f301	lavu/riscv: fix av_clip_int16 Some serious copy-paste / squash / rebase mismanipulation here. Signed-off-by: James Almer <jamrial@gmail.com>	2 years ago
Rémi Denis-Courmont	c177108ae1	lavu/riscv: add <intmath.h> optimisations This provides some micro-optimisations for signed integer clipping, and support for bit weight with the Zbb extension.	2 years ago
Rémi Denis-Courmont	df2057041b	lavu/riscv: byte-swap operations If the target supports the Basic bit-manipulation (Zbb) extension, then the REV8 instruction is available to reverse byte order. Note that this instruction only exists at the "XLEN" register size, so we need to right shift the result down to the data width. If Zbb is not supported, then this patchset does nothing. Support for run-time detection is left for the future. Currently, there are no bits in auxv/ELF HWCAP for Z-extensions, so there are no clean ways to do this.	2 years ago
Rémi Denis-Courmont	d808070547	lavu/riscv: AV_READ_TIME cycle counter This uses the architected RISC-V 64-bit cycle counter from the RISC-V unprivileged instruction set. In 64-bit and 128-bit, this is a straightforward CSR read. In 32-bit mode, the 64-bit value is exposed as two CSRs, which cannot be read atomically, so a loop is necessary to detect and fix up the race condition where the bottom half wraps exactly between the two reads.	2 years ago

21 Commits (c03f9654c997b33b8028eb71c9e7ba61fd53a813)