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${ noResults }
10 Commits (b72b212a4c43563f1b9fc3ce9a5ff91f89b857ac)
| Author | SHA1 | Message | Date |
|---|---|---|---|
Christophe Gisquet
|
4cb6964244 |
dcadec: simplify decoding of VQ high frequencies
The vector dequantization has a test in a loop preventing effective SIMD
implementation. By moving it out of the loop, this loop can be DSPized.
Therefore, modify the current DSP implementation. In particular, the
DSP implementation no longer has to handle null loop sizes.
The decode_hf implementations have following timings:
For x86 Arrandale:
C SSE SSE2 SSE4
win32: 260 162 119 104
win64: 242 N/A 89 72
The arm NEON optimizations follow in a later patch as external asm. The
now unused check for the y modifier in arm inline asm is removed from
configure.
|
11 years ago |
Janne Grunau
|
5c1c6e8226 |
dca: include dcadsp.h in {arm,x86}/dca.h for checkheaders
|
11 years ago |
|
Christophe Gisquet
|
2bd44cb705 |
dcadsp: add int8x8_fmul_int32 to dsp context
It is currently declared as a macro who is set to inlinable functions, among which a Neon and a default C implementations. Add a DSP parameter to each inline function, unused except by the default C implementation which calls a function from the DSP context. On an Arrandale CPU, gain for an inlined SSE2 function vs. a call: - Win32: 29 to 26 cycles - Win64: 25 to 23 cycles Signed-off-by: Janne Grunau <janne-libav@jannau.net> |
11 years ago |
|
Christophe Gisquet
|
b6293e2798 |
fmtconvert: Explicitly use int32_t instead of int
Signed-off-by: Martin Storsjö <martin@martin.st> |
12 years ago |
Diego Biurrun
|
76b19a3984 |
Fix a number of incorrect intmath.h #includes.
|
12 years ago |
Mans Rullgard
|
a7831d509f |
arm: use HAVE*_INLINE/EXTERNAL macros for conditional compilation
These macros reflect the actual capabilities required here. Signed-off-by: Mans Rullgard <mans@mansr.com> |
12 years ago |
|
Mans Rullgard
|
f7de52354f |
ARM: dca: disable optimised decode_blockcodes() for old gcc
Old gcc versions have trouble compiling this function, and no simple, targeted test is possible. Signed-off-by: Mans Rullgard <mans@mansr.com> |
13 years ago |
|
Mans Rullgard
|
00a856e3f9 |
dca: ARMv6 optimised decode_blockcode()
This is a hand-tuned version of the code with impossible parts of the FASTDIV function ommitted. 2-5% faster overall on Cortex-A8. Signed-off-by: Mans Rullgard <mans@mansr.com> |
13 years ago |
|
Mans Rullgard
|
6308729e68 |
ARM: check for inline asm 'y' operand modifier support
The inline asm added in
|
13 years ago |
|
Mans Rullgard
|
bf5d46d8e6 |
dca: NEON optimised high freq VQ decoding
Signed-off-by: Mans Rullgard <mans@mansr.com> |
13 years ago |