Introduce a new function to set binary data through AVOption,
avoiding having to convert the binary data to a string inbetween.
Signed-off-by: Martin Storsjö <martin@martin.st>
Just like gcc 4.6 and later on ARM, gcc 4.8 on MIPS generates
inefficient code when a known-unaligned location is used as a
memory input operand. This applies the same fix as has been
previously done to the ARM version of the code.
Signed-off-by: Mans Rullgard <mans@mansr.com>
GCC actually handles unaligned accesses correctly in all cases
except, absurdly, 32-bit loads on mips64. The remaining asm is
thus not needed, and removing it results in better code.
Signed-off-by: Mans Rullgard <mans@mansr.com>
libavcodec/utils.c:274: warning: passing argument 3 of ‘av_samples_fill_arrays’ discards qualifiers from pointer target type
./libavutil/samplefmt.h:151: note: expected ‘uint8_t *’ but argument is of type ‘const uint8_t *’
Commit adebad0 "arm: intreadwrite: fix inline asm constraints for gcc
4.6 and later" caused some older gcc versions to miscompile code.
This reverts to the old version of the code for these compilers.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Starting with version 4.7, gcc properly supports unaligned
memory accesses on ARM. Not using the inline asm with these
compilers results in better code.
Signed-off-by: Mans Rullgard <mans@mansr.com>
With a dereferenced type-cast pointer as memory operand, gcc 4.6
and later will sometimes copy the data to a temporary location,
the address of which is used as the operand value, if it thinks
the target address might be misaligned. Using a pointer to a
packed struct type instead does the right thing.
The 16-bit case is special since the ldrh instruction addressing
modes are limited compared to ldr. The "Uq" constraint produces a
memory reference suitable for an ldrsb instruction, which supports
the same addressing modes as ldrh. However, the restrictions appear
to apply only when the operand addresses a single byte. The memory
reference must thus be split into two operands each targeting one
byte. Finally, the "Uq" constraint is only available in ARM mode.
The Thumb-2 ldrh instruction supports most addressing modes so the
normal "m" constraint can be used there.
Signed-off-by: Mans Rullgard <mans@mansr.com>
This allows masking CPU features with the -cpuflags avconv option
which is useful for testing different optimisations without rebuilding.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Add support for all x86-64 registers
Prefer caller-saved register over callee-saved on WIN64
Support up to 15 function arguments
Also (by Ronald S. Bultje)
Fix up our asm to work with new x86inc.asm.
Signed-off-by: Ronald S. Bultje <rsbultje@gmail.com>
Signed-off-by: Justin Ruggles <justin.ruggles@gmail.com>
Plain POSIX malloc(0) is allowed to return either NULL or a
non-NULL pointer. The calling code should be ready to handle
a NULL return as a correct return (instead of a failure) if the size
to allocate was 0 - this makes sure the condition is handled
in a consistent way across platforms.
This also avoids calling posix_memalign(&ptr, 32, 0) on OS X,
which returns an invalid pointer (a non-NULL pointer that causes
crashes when passed to av_free).
Abort in debug mode, to help track down issues related to
incorrect handling of this case.
Signed-off-by: Martin Storsjö <martin@martin.st>
Signed-off-by: Nicolas George <nicolas.george@normalesup.org>
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
Signed-off-by: Justin Ruggles <justin.ruggles@gmail.com>
The were broken since August of 2010 without anyone noticing until
three weeks ago. Nobody cares about it anymore and hopefully Marvell
will support NEON like in the PXA978 from now on.
Justin Ruggles
Mans Rullgard
Vitor Sessak
Anton Khirnov
Samuel Pitoiset
Diego Biurrun
Loren Merritt
Henrik Gramner
Martin Storsjö
Nicolas George
Ronald S. Bultje
Janne Grunau