FFmpeg

Commit Graph

Author	SHA1	Message	Date
Rémi Denis-Courmont	f2c30fe15a	lavc/riscv: add forward-edge CFI landing pads	5 months ago
Rémi Denis-Courmont	187d4d066a	lavc/riscv: require B or zba explicitly	5 months ago
Rémi Denis-Courmont	d076517056	lavc/llauddsp: R-V V scalarproduct_and_madd_int32 scalarproduct_and_madd_int32_c: 10899.7 scalarproduct_and_madd_int32_rvv_i32: 1749.0	1 year ago
Rémi Denis-Courmont	45d0eb3f70	lavc/llauddsp: R-V V scalarproduct_and_madd_int16 scalarproduct_and_madd_int16_c: 10355.7 scalarproduct_and_madd_int16_rvv_i32: 1480.0	1 year ago
Rémi Denis-Courmont	90a779bed6	lavc/huffyuvdsp: basic R-V V add_hfyu_left_pred_bgr32 Better performance can probably be achieved with a more intricate unrolled loop, but this is a start: add_hfyu_left_pred_bgr32_c: 15084.0 add_hfyu_left_pred_bgr32_rvv_i32: 10280.2 This would actually be cleaner with the RISC-V P extension, but that is not ratified yet (I think?) and usually not supported if V is supported.	1 year ago
Rémi Denis-Courmont	424c8ceb08	lavc/huffyuvdsp: R-V V add_int16 add_int16_128_c: 2390.5 add_int16_128_rvv_i32: 832.0 add_int16_rnd_width_c: 2390.2 add_int16_rnd_width_rvv_i32: 832.5	1 year ago
Rémi Denis-Courmont	3c6516330f	lavc/exrdsp: R-V V reoder_pixels	1 year ago
Rémi Denis-Courmont	61e5ca4ded	lavc/bswapdsp: purge RISC-V V bswap32 This cannot beat the Zbb implementation, and it is unlikely that a real meaningful CPU design would support V and not Zbb. The best loop rewrite that I could come up with (4 shifts, 2 ands, 3 ors) is still ~40% slower than Zbb. A proper faster vector implementation should be feasible with the cryptographic vector extensions, but that is a story for another time.	1 year ago
Rémi Denis-Courmont	5de1db5370	lavc/bswapdsp: rewrite RISC-V V bswap16 This favours bit-wise logic over slow strided stores.	1 year ago
Rémi Denis-Courmont	2abafd7307	lavc/bswapdsp: RISC-V V bswap16_buf	2 years ago
Rémi Denis-Courmont	d7528af4df	lavc/bswapdsp: RISC-V V bswap_buf	2 years ago
Rémi Denis-Courmont	3ba5579e55	riscv: remove unnecessary #include's Pointed out by Andreas Rheinhardt.	2 years ago
Martin Storsjö	dd2e524ffa	riscv: Use the correct path for including asm.S Signed-off-by: Martin Storsjö <martin@martin.st>	2 years ago
Rémi Denis-Courmont	453aba71e6	lavc/vorbisdsp: RISC-V V inverse_coupling This uses the following vectorisation: for (i = 0; i < blocksize; i++) { ang[i] = mag[i] - copysignf(fmaxf(ang[i], 0.f), mag[i]); mag[i] = mag[i] - copysignf(fminf(ang[i], 0.f), mag[i]); }	2 years ago
Rémi Denis-Courmont	c1bb19e263	lavu/fixeddsp: RISC-V V butterflies_fixed	2 years ago
Rémi Denis-Courmont	04d092e7d5	lavc/audiodsp: RISC-V F vector_clipf RV64G supports MIN & MAX instructions natively only on floating point registers, not general purpose ones. The later would require the Zbb extension. Due to that, it is actually faster to perform the clipping "properly" in FPU. Benchmarks on SiFive U74-MC (courtesy of Shanghai StarFive Tech): audiodsp.vector_clipf_c: 29551.5 audiodsp.vector_clipf_rvf: 17871.0 Also tried unrolling with 2 or 8 elements but it gets worse either way.	2 years ago
Diego Biurrun	9a9e2f1c8a	dsputil: Split audio operations off into a separate context	11 years ago
Ben Avison	9d8ecdd8ca	vc-1: Add platform-specific start code search routine to VC1DSPContext. Initialise VC1DSPContext for parser as well as for decoder. Note, the VC-1 code doesn't actually use the function pointer yet. Signed-off-by: Michael Niedermayer <michaelni@gmx.at>	11 years ago
Mason Carter	832e190632	vc1: arm: Add NEON assembly For: ff_vc1_inv_trans_{8,4}x{8,4}_{dc_,}neon ff_put_pixels8x8_neon ff_put_vc1_mspel_mc{0,1,2,3}{0,1,2,3}_neon (except for 00) Based on ARM assembly code in libavcodec/arm by Rob Clark and Mans Rullgard. Signed-off-by: Martin Storsjö <martin@martin.st>	11 years ago
Diego Biurrun	73b704ac60	arm: Add some missing header #includes	12 years ago
Mans Rullgard	b692d246ea	vp8: arm: separate ARMv6 functions from NEON This is a preparation for complete ARMv6 optimisations. Signed-off-by: Mans Rullgard <mans@mansr.com>	13 years ago
Mans Rullgard	d526c5338d	ARM: allow runtime masking of CPU features This allows masking CPU features with the -cpuflags avconv option which is useful for testing different optimisations without rebuilding. Signed-off-by: Mans Rullgard <mans@mansr.com>	13 years ago
Michael Niedermayer	c266eb1928	arm: Fix 10l typo Signed-off-by: Michael Niedermayer <michaelni@gmx.at>	13 years ago
Ronald S. Bultje	bd66f073fe	vp8: change int stride to ptrdiff_t stride. On 64bit platforms with 32bit int, this means we won't have to sign- extend the integer anymore.	13 years ago
Diego Biurrun	32f3c541bc	doxygen: Do not include license boilerplates in Doxygen comment blocks.	13 years ago
Ronald S. Bultje	a5dfeb612e	VP8: armv6 optimizations. From 52.503s (~40fps) to 27.973sec (~80fps) decoding of 480p sintel trailer, i.e. a ~2x speedup overall, on a Nexus S. Signed-off-by: Michael Niedermayer <michaelni@gmx.at>	13 years ago
Mans Rullgard	2912e87a6c	Replace FFmpeg with Libav in licence headers Signed-off-by: Mans Rullgard <mans@mansr.com>	14 years ago
Mans Rullgard	ef15d71c1f	VP8: ARM NEON optimisations for dsp functions This adds NEON optimised versions of all functions in VP8DSPContext. Based on initial work by Rob Clark. Signed-off-by: Mans Rullgard <mans@mansr.com> (cherry picked from commit `a1c1d3c003`)	14 years ago
Mans Rullgard	a1c1d3c003	VP8: ARM NEON optimisations for dsp functions This adds NEON optimised versions of all functions in VP8DSPContext. Based on initial work by Rob Clark. Signed-off-by: Mans Rullgard <mans@mansr.com>	14 years ago

4 Commits (95c9c1c2becd11570359873c0698ed78f33e3693)