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N
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${ noResults }
4 Commits (869c06886dfdbc5d4734bb8f4ee85f36b2f3aa2b)
Author | SHA1 | Message | Date |
---|---|---|---|
Rémi Denis-Courmont | f59a767ccd |
lavu/riscv: helper macro for VTYPE encoding
On most cases, the vector type (VTYPE) for the RISC-V Vector extension is supplied as an immediate value, with either of the VSETVLI or VSETIVLI instructions. There is however a third instruction VSETVL which takes the vector type from a general purpose register. That is so the type can be selected at run-time. This introduces a macro to load a (valid) vector type into a register. The syntax follows that of VSETVLI and VSETIVLI, with element size, group multiplier, then tail and mask policies. |
2 years ago |
Rémi Denis-Courmont | 3ba5579e55 |
riscv: remove unnecessary #include's
Pointed out by Andreas Rheinhardt. |
2 years ago |
Rémi Denis-Courmont | 39357cad37 |
lavu/riscv: fallback macros for SH{1, 2, 3}ADD
Those mnemonics require the very latest binutils release at the time of writing. These macros provide seamless backward compatibility. |
2 years ago |
Rémi Denis-Courmont | 746f1ff36a |
lavu/riscv: initial common header for assembler macros
|
2 years ago |