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Commit Graph

3 Commits (7bb5626fa7754b37932dfa11d497b7101c55291a)

Author	SHA1	Message	Date
Rémi Denis-Courmont	4f2472909e	sws/riscv: add forward-edge CFI landing pads	6 months ago
Rémi Denis-Courmont	e91a8cc4de	sws/riscv: require B or zba explicitly	6 months ago
Rémi Denis-Courmont	c4a144c29d	swscale/rgb2rgb: add R-V Zbb shuffle_bytes_3210	1 year ago
Rémi Denis-Courmont	cec48e3b32	riscv: factor out the bswap32 assembler	1 year ago
Rémi Denis-Courmont	f0ef11ea83	lavc/bswapdsp: RISC-V B bswap_buf ... Simply taking the Zbb REV8 instruction into use in a simple loop gives some significant savings: bswap_buf_c: 1081.0 bswap_buf_rvb_b: 771.0 But we can also use the 64-bit REV8 as a pseudo-SIMD instruction with just one additional shift, and one fewer load, effectively doubling the bandwidth. Consequently, this patch is useful even if the compile-time target has Zbb enabled for C code: bswap_buf_c: 1081.0 bswap_buf_rvb_b: 341.0 (this patch) On the other hand, this approach fails miserably for bswap16_buf as the ratio of shifts and stores becomes unfavorable compared to naïve C: bswap16_buf_c: 1542.0 bswap16_buf_rvb_b: 1803.7 Unrolling to process 128 bits (4 samples) at a time actually worsens performance ever so slightly: bswap_buf_c: 1081.0 bswap_buf_rvb_b: 408.5	2 years ago