6 Commits (7aa6510fe1fc726f0acd22c5b2d2537c69099395)

Author SHA1 Message Date
Rémi Denis-Courmont 01c5f4ad9f riscv: add Zvbb vector bit manipulation extension 9 months ago
Rémi Denis-Courmont b3825bbe45 riscv: test for assembler support 1 year ago
Rémi Denis-Courmont 1b6aee52a5 configure: probe RISC-V Vector extension 2 years ago
Shiyou Yin 9a840ffa17 avutil: [loongarch] Add support for loongarch SIMD. 3 years ago
Diego Biurrun fd502f4f5f build: Generalize yasm/nasm-related variable names 8 years ago