14 Commits (6f8e365a2af2b6b21701d41eed3b2e3f8a436eeb)

Author SHA1 Message Date
Rémi Denis-Courmont 6319601343 lavu/riscv: assembly for zicfilp LPAD 5 months ago
Rémi Denis-Courmont 982376660c lavu/riscv: align functions to 4 bytes 5 months ago
Rémi Denis-Courmont 529d423012 lavu/riscv: remove bespoke SH{1,2,3}ADD assembler 5 months ago
Rémi Denis-Courmont 7f97344bfb lavu/riscv: grok B as an extension 5 months ago
Rémi Denis-Courmont 1e7ab200ee lavu/riscv: allow any number of extensions 5 months ago
Rémi Denis-Courmont 4fe8f2cc43 riscv: allow passing addend to vtype_vli macro 7 months ago
Rémi Denis-Courmont ee1526c05f lavu/riscv: add assembler macros for adjusting vector LMUL 8 months ago
Rémi Denis-Courmont 5afe734b6d lavu/riscv: remove bespoke assembler for MIN 8 months ago
Rémi Denis-Courmont 89029baebd lavu/riscv: allow requesting a second extension 8 months ago
Rémi Denis-Courmont cd6089dc9c riscv: fix builds without Zbb support 1 year ago
Rémi Denis-Courmont f59a767ccd lavu/riscv: helper macro for VTYPE encoding 2 years ago
Rémi Denis-Courmont 3ba5579e55 riscv: remove unnecessary #include's 2 years ago
Rémi Denis-Courmont 39357cad37 lavu/riscv: fallback macros for SH{1, 2, 3}ADD 2 years ago
Rémi Denis-Courmont 746f1ff36a lavu/riscv: initial common header for assembler macros 2 years ago