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${ noResults }
5 Commits (455fcf29b8482009d2ad13da56cd1122973dc858)
| Author | SHA1 | Message | Date |
|---|---|---|---|
Christophe GISQUET
|
2130bd8f5b |
rv40dsp x86: use only one register, for both increment and loop counter
Around 10 cycles faster for luma. Signed-off-by: Ronald S. Bultje <rsbultje@gmail.com> |
13 years ago |
|
Christophe GISQUET
|
272b252c01 |
rv40dsp: implement prescaled versions for biweight.
Quite often, the original weights are multiple of 512. By prescaling them by 1/512 when they are computed (once per frame), no intermediate shifting is needed, and no prescaling on each call either. The x86 code already used that trick. Signed-off-by: Ronald S. Bultje <rsbultje@gmail.com> |
13 years ago |
Reimar Döffinger
|
da1ba4e88b |
Fix NASM compilation.
movd needs explicit register size prefix for NASM. Signed-off-by: Reimar Döffinger <Reimar.Doeffinger@gmx.de> |
13 years ago |
|
Christophe Gisquet
|
e5c9de2ab7 |
rv40: x86 SIMD for biweight
Provide MMX, SSE2 and SSSE3 versions, with a fast-path when the weights are multiples of 512 (which is often the case when the values round up nicely). *_TIMER report for the 16x16 and 8x8 cases: C: 9015 decicycles in 16, 524257 runs, 31 skips 2656 decicycles in 8, 524271 runs, 17 skips MMX: 4156 decicycles in 16, 262090 runs, 54 skips 1206 decicycles in 8, 262131 runs, 13 skips MMX on fast-path: 2760 decicycles in 16, 524222 runs, 66 skips 995 decicycles in 8, 524252 runs, 36 skips SSE2: 2163 decicycles in 16, 262131 runs, 13 skips 832 decicycles in 8, 262137 runs, 7 skips SSE2 with fast path: 1783 decicycles in 16, 524276 runs, 12 skips 711 decicycles in 8, 524283 runs, 5 skips SSSE3: 2117 decicycles in 16, 262136 runs, 8 skips 814 decicycles in 8, 262143 runs, 1 skips SSSE3 with fast path: 1315 decicycles in 16, 524285 runs, 3 skips 578 decicycles in 8, 524286 runs, 2 skips This means around a 4% speedup for some sequences. Signed-off-by: Diego Biurrun <diego@biurrun.de> |
13 years ago |