Tag: Branch: Tree: 2e46d68f55

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Commit Graph

6 Commits (2e46d68f553c36f61e46f1db5c5adce84b60f175)

Author	SHA1	Message	Date
Rémi Denis-Courmont	01c5f4ad9f	riscv: add Zvbb vector bit manipulation extension	9 months ago
Rémi Denis-Courmont	b3825bbe45	riscv: test for assembler support ... This should fix the build on LLVM 16 and earlier, at the cost of turning all non-RVV optimisations off.	1 year ago
Rémi Denis-Courmont	1b6aee52a5	configure: probe RISC-V Vector extension	2 years ago
Shiyou Yin	9a840ffa17	avutil: [loongarch] Add support for loongarch SIMD. ... LSX and LASX is loongarch SIMD extention. They are enabled by default if compiler support it, and can be disabled with '--disable-lsx' '--disable-lasx'. Change-Id: Ie2608ea61dbd9b7fffadbf0ec2348bad6c124476 Reviewed-by: Shiyou Yin <yinshiyou-hf@loongson.cn> Reviewed-by: guxiwei <guxiwei-hf@loongson.cn> Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>	3 years ago
Diego Biurrun	fd502f4f5f	build: Generalize yasm/nasm-related variable names ... None of them are specific to the YASM assembler. (Cherry-picked from libav commit 39e208f4d4) Signed-off-by: James Almer <jamrial@gmail.com>	8 years ago