mirror of https://github.com/FFmpeg/FFmpeg.git
on ev6. Originally committed as revision 979 to svn://svn.ffmpeg.org/ffmpeg/trunkpull/126/head
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/* |
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* Alpha optimized DSP utils |
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* Copyright (c) 2002 Falk Hueffner <falk@debian.org>
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* |
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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#include "regdef.h" |
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#ifdef HAVE_AV_CONFIG_H
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#include "config.h" |
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#endif |
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/* Some nicer register names. */ |
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#define ta t10 |
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#define tb t11 |
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#define tc t12 |
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#define td AT |
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/* Danger: these overlap with the argument list and the return value */ |
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#define te a5 |
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#define tf a4 |
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#define tg a3 |
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#define th v0 |
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.set noat
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.set noreorder
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.arch pca56
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.text |
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/***************************************************************************** |
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* int pix_abs16x16_mvi_asm(uint8_t *pix1, uint8_t *pix2, int line_size) |
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* |
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* This code is written with a pca56 in mind. For ev6, one should |
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* really take the increased latency of 3 cycles for MVI instructions |
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* into account. |
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* |
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* It is important to keep the loading and first use of a register as |
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* far apart as possible, because if a register is accessed before it |
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* has been fetched from memory, the CPU will stall. |
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*/ |
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.align 4
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.globl pix_abs16x16_mvi_asm
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.ent pix_abs16x16_mvi_asm
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pix_abs16x16_mvi_asm: |
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.frame sp, 0, ra, 0 |
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.prologue 0
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#ifdef HAVE_GPROF |
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lda AT, _mcount |
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jsr AT, (AT), _mcount |
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#endif |
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and a1, 7, t0 |
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clr v0 |
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lda a3, 16 |
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beq t0, $aligned |
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.align 4
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$unaligned: |
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/* Registers: |
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line 0: |
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t0: left_u -> left lo -> left |
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t1: mid |
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t2: right_u -> right hi -> right |
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t3: ref left |
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t4: ref right |
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line 1: |
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t5: left_u -> left lo -> left |
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t6: mid |
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t7: right_u -> right hi -> right |
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t8: ref left |
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t9: ref right |
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temp: |
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ta: left hi |
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tb: right lo |
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tc: error left |
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td: error right */ |
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/* load line 0 */ |
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ldq_u t0, 0(a1) # left_u |
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ldq_u t1, 8(a1) # mid |
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ldq_u t2, 16(a1) # right_u |
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ldq t3, 0(a0) # ref left |
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ldq t4, 8(a0) # ref right |
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addq a0, a2, a0 # pix1 |
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addq a1, a2, a1 # pix2 |
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/* load line 1 */
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ldq_u t5, 0(a1) # left_u |
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ldq_u t6, 8(a1) # mid |
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ldq_u t7, 16(a1) # right_u |
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ldq t8, 0(a0) # ref left |
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ldq t9, 8(a0) # ref right |
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addq a0, a2, a0 # pix1 |
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addq a1, a2, a1 # pix2 |
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/* calc line 0 */ |
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extql t0, a1, t0 # left lo |
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extqh t1, a1, ta # left hi |
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extql t1, a1, tb # right lo |
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or t0, ta, t0 # left |
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extqh t2, a1, t2 # right hi |
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perr t3, t0, tc # error left |
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or t2, tb, t2 # right |
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perr t4, t2, td # error right |
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addq v0, tc, v0 # add error left |
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addq v0, td, v0 # add error left |
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/* calc line 1 */ |
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extql t5, a1, t5 # left lo |
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extqh t6, a1, ta # left hi |
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extql t6, a1, tb # right lo |
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or t5, ta, t5 # left |
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extqh t7, a1, t7 # right hi |
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perr t8, t5, tc # error left |
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or t7, tb, t7 # right |
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perr t9, t7, td # error right |
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addq v0, tc, v0 # add error left |
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addq v0, td, v0 # add error left |
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/* loop */ |
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subq a3, 2, a3 # h -= 2 |
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bne a3, $unaligned |
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ret |
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.align 4
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$aligned: |
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/* load line 0 */ |
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ldq t0, 0(a1) # left |
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ldq t1, 8(a1) # right |
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addq a1, a2, a1 # pix2 |
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ldq t2, 0(a0) # ref left |
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ldq t3, 8(a0) # ref right |
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addq a0, a2, a0 # pix1 |
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/* load line 1 */ |
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ldq t4, 0(a1) # left |
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ldq t5, 8(a1) # right |
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addq a1, a2, a1 # pix2 |
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ldq t6, 0(a0) # ref left |
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ldq t7, 8(a0) # ref right |
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addq a0, a2, a0 # pix1 |
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/* load line 2 */ |
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ldq t8, 0(a1) # left |
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ldq t9, 8(a1) # right |
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addq a1, a2, a1 # pix2 |
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ldq ta, 0(a0) # ref left |
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ldq tb, 8(a0) # ref right |
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addq a0, a2, a0 # pix1 |
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/* load line 3 */ |
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ldq tc, 0(a1) # left |
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ldq td, 8(a1) # right |
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addq a1, a2, a1 # pix2 |
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ldq te, 0(a0) # ref left |
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ldq tf, 8(a0) # ref right |
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/* calc line 0 */ |
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perr t0, t2, t0 # error left |
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addq a0, a2, a0 # pix1 |
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perr t1, t3, t1 # error right |
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addq v0, t0, v0 # add error left |
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/* calc line 1 */ |
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perr t4, t6, t0 # error left |
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addq v0, t1, v0 # add error right |
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perr t5, t7, t1 # error right |
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addq v0, t0, v0 # add error left |
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/* calc line 2 */ |
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perr t8, ta, t0 # error left |
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addq v0, t1, v0 # add error right |
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perr t9, tb, t1 # error right |
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addq v0, t0, v0 # add error left |
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/* calc line 3 */ |
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perr tc, te, t0 # error left |
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addq v0, t1, v0 # add error right |
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perr td, tf, t1 # error right |
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addq v0, t0, v0 # add error left |
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addq v0, t1, v0 # add error right |
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/* loop */ |
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subq a3, 4, a3 # h -= 4 |
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bne a3, $aligned |
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ret |
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.end pix_abs16x16_mvi_asm
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