lavc/riscv: don't set vxrm if unnecessary

While narrowing clip is nominally a rounding operation, the rounding mode
has no arithmetic consequence if the right shift is by zero bits.
release/7.1
Rémi Denis-Courmont 6 months ago
parent e42a0763b7
commit bbfc0ac9ca
  1. 5
      libavcodec/riscv/h263dsp_rvv.S
  2. 1
      libavcodec/riscv/vp8dsp_rvv.S

@ -31,14 +31,13 @@ func ff_h263_h_loop_filter_rvv, zve32x
vssseg4e8.v v8, (a0), a1 vssseg4e8.v v8, (a0), a1
ret ret
1: 1:
csrwi vxrm, 0 auipc t1, %pcrel_hi(ff_h263_loop_filter_strength)
2: auipc t1, %pcrel_hi(ff_h263_loop_filter_strength)
vwsubu.vv v14, v10, v9 # p2 - p1 vwsubu.vv v14, v10, v9 # p2 - p1
add t1, t1, a2 add t1, t1, a2
vwsubu.vv v12, v8, v11 # p0 - p3 vwsubu.vv v12, v8, v11 # p0 - p3
vsetvli zero, zero, e16, m1, ta, mu vsetvli zero, zero, e16, m1, ta, mu
vsll.vi v14, v14, 2 vsll.vi v14, v14, 2
lbu t1, %pcrel_lo(2b)(t1) # strength lbu t1, %pcrel_lo(1b)(t1) # strength
vadd.vv v16, v12, v14 vadd.vv v16, v12, v14
# Divide by 8 toward 0. v16 is a signed 10-bit value at this point. # Divide by 8 toward 0. v16 is a signed 10-bit value at this point.
vsrl.vi v18, v16, 16 - 3 # v18 = (v16 < 0) ? 7 : 0 vsrl.vi v18, v16, 16 - 3 # v18 = (v16 < 0) ? 7 : 0

@ -169,7 +169,6 @@ endfunc
# a3 = DC # a3 = DC
func ff_vp78_idct_dc_add_rvv, zve32x func ff_vp78_idct_dc_add_rvv, zve32x
csrwi vxrm, 0
vsetivli zero, 4, e8, mf4, ta, ma vsetivli zero, 4, e8, mf4, ta, ma
sh zero, (a1) sh zero, (a1)
vlse32.v v8, (a0), a2 vlse32.v v8, (a0), a2

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