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@ -57,7 +57,8 @@ static unsigned char* perfname[] = { |
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"put_no_rnd_pixels8_xy2_altivec", |
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"put_pixels16_xy2_altivec", |
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"put_no_rnd_pixels16_xy2_altivec", |
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"clear_blocks_dcbz32_ppc" |
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"clear_blocks_dcbz32_ppc", |
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"clear_blocks_dcbz128_ppc" |
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}; |
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#ifdef POWERPC_PERF_USE_PMC |
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unsigned long long perfdata_miss[powerpc_perf_total][powerpc_data_total]; |
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@ -110,6 +111,18 @@ void powerpc_display_perf_report(void) |
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It simply clear to zero a single cache line, |
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so you need to know the cache line size to use it ! |
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It's absurd, but it's fast... |
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update 24/06/2003 : Apple released yesterday the G5, |
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with a PPC970. cache line size : 128 bytes. Oups. |
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The semantic of dcbz was changed, it always clear |
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32 bytes. so the function below will work, but will |
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be slow. So I fixed check_dcbz_effect to use dcbzl, |
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which is defined to clear a cache line (as dcbz before). |
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So we still can distinguish, and use dcbz (32 bytes) |
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or dcbzl (one cache line) as required. |
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see <http://developer.apple.com/technotes/tn/tn2087.html>
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and <http://developer.apple.com/technotes/tn/tn2086.html>
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*/ |
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void clear_blocks_dcbz32_ppc(DCTELEM *blocks) |
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{ |
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@ -126,7 +139,7 @@ POWERPC_TBL_START_COUNT(powerpc_clear_blocks_dcbz32, 1); |
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i += 16; |
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} |
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for ( ; i < sizeof(DCTELEM)*6*64 ; i += 32) { |
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asm volatile("dcbz %0,%1" : : "r" (blocks), "r" (i) : "memory"); |
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asm volatile("dcbz %0,%1" : : "r" (i), "r" (blocks) : "memory"); |
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} |
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if (misal) { |
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((unsigned long*)blocks)[188] = 0L; |
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@ -141,8 +154,45 @@ POWERPC_TBL_START_COUNT(powerpc_clear_blocks_dcbz32, 1); |
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POWERPC_TBL_STOP_COUNT(powerpc_clear_blocks_dcbz32, 1); |
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} |
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/* same as above, when dcbzl clear a whole 128B cache line
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i.e. the PPC970 aka G5 */ |
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#ifndef NO_DCBZL |
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void clear_blocks_dcbz128_ppc(DCTELEM *blocks) |
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{ |
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POWERPC_TBL_DECLARE(powerpc_clear_blocks_dcbz128, 1); |
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register int misal = ((unsigned long)blocks & 0x0000007f); |
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register int i = 0; |
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POWERPC_TBL_START_COUNT(powerpc_clear_blocks_dcbz128, 1); |
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#if 1 |
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if (misal) { |
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// we could probably also optimize this case,
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// but there's not much point as the machines
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// aren't available yet (2003-06-26)
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memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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} |
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else |
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for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) { |
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asm volatile("dcbzl %0,%1" : : "r" (i), "r" (blocks) : "memory"); |
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} |
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#else |
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memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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#endif |
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POWERPC_TBL_STOP_COUNT(powerpc_clear_blocks_dcbz128, 1); |
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} |
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#else |
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void clear_blocks_dcbz128_ppc(DCTELEM *blocks) |
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{ |
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memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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} |
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#endif |
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#ifndef NO_DCBZL |
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/* check dcbz report how many bytes are set to 0 by dcbz */ |
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long check_dcbz_effect(void) |
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/* update 24/06/2003 : replace dcbz by dcbzl to get
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the intended effect (Apple "fixed" dcbz) |
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unfortunately this cannot be used unless the assembler |
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knows about dcbzl ... */ |
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long check_dcbzl_effect(void) |
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{ |
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register char *fakedata = (char*)av_malloc(1024); |
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register char *fakedata_middle; |
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@ -159,7 +209,7 @@ long check_dcbz_effect(void) |
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memset(fakedata, 0xFF, 1024); |
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asm volatile("dcbz %0, %1" : : "r" (fakedata_middle), "r" (zero)); |
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asm volatile("dcbzl %0, %1" : : "r" (fakedata_middle), "r" (zero)); |
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for (i = 0; i < 1024 ; i ++) |
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{ |
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@ -171,15 +221,24 @@ long check_dcbz_effect(void) |
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return count; |
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} |
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#else |
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long check_dcbzl_effect(void) |
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{ |
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return 0; |
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} |
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#endif |
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void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx) |
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{ |
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// Common optimisations whether Altivec or not
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// Common optimizations whether Altivec is available or not
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switch (check_dcbz_effect()) { |
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switch (check_dcbzl_effect()) { |
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case 32: |
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c->clear_blocks = clear_blocks_dcbz32_ppc; |
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break; |
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case 128: |
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c->clear_blocks = clear_blocks_dcbz128_ppc; |
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break; |
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default: |
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break; |
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} |
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Michael Niedermayer
22 years ago