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ARM: swap source operands in some add instructions

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This allows using a 16-bit opcode when generating Thumb2 code.

Signed-off-by: Mans Rullgard <mans@mansr.com>
release/1.0
Mans Rullgard 13 years ago
parent 0122118ec3
commit a27a690fac
4 changed files with 7 additions and 7 deletions
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  1. 2
      libavcodec/arm/ac3dsp_armv6.S
  2. 4
      libavcodec/arm/dsputil_arm.S
  3. 6
      libavcodec/arm/vp8_armv6.S
  4. 2
      libavutil/arm/asm.S

2
libavcodec/arm/ac3dsp_armv6.S
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@ -32,7 +32,7 @@ function ff_ac3_bit_alloc_calc_bap_armv6, export=1
ldrb r4, [r4, r2]
add r1, r1, r2, lsl #1 @ psd + start
add r0, r0, r4, lsl #1 @ mask + band
add r4, lr, r4
add r4, r4, lr
add r7, r7, r2 @ bap + start
1:
ldrsh r9, [r0], #2 @ mask[band]

4
libavcodec/arm/dsputil_arm.S
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@ -632,7 +632,7 @@ function ff_add_pixels_clamped_arm, export=1
ldrsh r7, [r0, #2]
and r6, r4, #0xFF
and r8, r4, #0xFF00
add r6, r5, r6
add r6, r6, r5
add r8, r7, r8, lsr #8
mvn r5, r5
mvn r7, r7
@ -674,7 +674,7 @@ function ff_add_pixels_clamped_arm, export=1
ldrsh r7, [r0, #10]
and r6, r4, #0xFF
and r8, r4, #0xFF00
add r6, r5, r6
add r6, r6, r5
add r8, r7, r8, lsr #8
mvn r5, r5
mvn r7, r7

6
libavcodec/arm/vp8_armv6.S
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@ -88,7 +88,7 @@ function ff_decode_block_coeffs_armv6, export=1
add r4, r3, r3, lsl #5
sxth r12, r11
add r4, r2, r4
add r4, r4, r2
adds r6, r6, r9
add r4, r4, #11
lsl r8, r8, r9
@ -138,7 +138,7 @@ A orrcs r8, r8, r10, lsl r6
2:
add r4, r3, r3, lsl #5
cmp r3, #16
add r4, r2, r4
add r4, r4, r2
pkhtb r11, r11, r11, asr #16
bne 0b
b 6b
@ -226,7 +226,7 @@ A orrcs r8, r8, r10, lsl r6
ldr r1, [sp, #4]
4:
add r4, r3, r3, lsl #5
add r4, r2, r4
add r4, r4, r2
add r4, r4, #22
rac_get_128 r5, r6, r7, r8, r9, r10
it ge

2
libavutil/arm/asm.S
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@ -142,7 +142,7 @@ ELF .size \name, . - \name
.if \indir
ldr \rd, [pc, \rd]
.else
add \rd, pc, \rd
add \rd, \rd, pc
.endif
def_pic \val - (.Lpic\@ + (8 >> CONFIG_THUMB)), .Lpicoff\@
.endm

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