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@ -1,6 +1,7 @@ |
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;****************************************************************************** |
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;****************************************************************************** |
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;* FFT transform with SSE/3DNow optimizations |
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;* FFT transform with SSE/3DNow optimizations |
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;* Copyright (c) 2008 Loren Merritt |
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;* Copyright (c) 2008 Loren Merritt |
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;* Copyright (c) 2011 Vitor Sessak |
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;* |
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;* |
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;* This algorithm (though not any of the implementation details) is |
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;* This algorithm (though not any of the implementation details) is |
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;* based on libdjbfft by D. J. Bernstein. |
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;* based on libdjbfft by D. J. Bernstein. |
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@ -49,9 +50,21 @@ endstruc |
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SECTION_RODATA |
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SECTION_RODATA |
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%define M_SQRT1_2 0.70710678118654752440 |
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%define M_SQRT1_2 0.70710678118654752440 |
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ps_root2: times 4 dd M_SQRT1_2 |
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%define M_COS_PI_1_8 0.923879532511287 |
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ps_root2mppm: dd -M_SQRT1_2, M_SQRT1_2, M_SQRT1_2, -M_SQRT1_2 |
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%define M_COS_PI_3_8 0.38268343236509 |
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ps_p1p1m1p1: dd 0, 0, 1<<31, 0 |
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align 32 |
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ps_cos16_1: dd 1.0, M_COS_PI_1_8, M_SQRT1_2, M_COS_PI_3_8, 1.0, M_COS_PI_1_8, M_SQRT1_2, M_COS_PI_3_8 |
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ps_cos16_2: dd 0, M_COS_PI_3_8, M_SQRT1_2, M_COS_PI_1_8, 0, -M_COS_PI_3_8, -M_SQRT1_2, -M_COS_PI_1_8 |
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ps_root2: times 8 dd M_SQRT1_2 |
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ps_root2mppm: dd -M_SQRT1_2, M_SQRT1_2, M_SQRT1_2, -M_SQRT1_2, -M_SQRT1_2, M_SQRT1_2, M_SQRT1_2, -M_SQRT1_2 |
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ps_p1p1m1p1: dd 0, 0, 1<<31, 0, 0, 0, 1<<31, 0 |
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perm1: dd 0x00, 0x02, 0x03, 0x01, 0x03, 0x00, 0x02, 0x01 |
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perm2: dd 0x00, 0x01, 0x02, 0x03, 0x01, 0x00, 0x02, 0x03 |
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ps_p1p1m1p1root2: dd 1.0, 1.0, -1.0, 1.0, M_SQRT1_2, M_SQRT1_2, M_SQRT1_2, M_SQRT1_2 |
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ps_m1m1p1m1p1m1m1m1: dd 1<<31, 1<<31, 0, 1<<31, 0, 1<<31, 1<<31, 1<<31 |
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ps_m1p1: dd 1<<31, 0 |
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ps_m1p1: dd 1<<31, 0 |
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%assign i 16 |
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%assign i 16 |
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@ -96,51 +109,80 @@ section .text align=16 |
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SWAP %3, %6 |
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SWAP %3, %6 |
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%endmacro |
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%endmacro |
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; in: %1 = {r0,i0,r2,i2,r4,i4,r6,i6} |
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; %2 = {r1,i1,r3,i3,r5,i5,r7,i7} |
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; %3, %4, %5 tmp |
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; out: %1 = {r0,r1,r2,r3,i0,i1,i2,i3} |
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; %2 = {r4,r5,r6,r7,i4,i5,i6,i7} |
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%macro T8_AVX 5 |
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vsubps %5, %1, %2 ; v = %1 - %2 |
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vaddps %3, %1, %2 ; w = %1 + %2 |
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vmulps %2, %5, [ps_p1p1m1p1root2] ; v *= vals1 |
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vpermilps %2, %2, [perm1] |
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vblendps %1, %2, %3, 0x33 ; q = {w1,w2,v4,v2,w5,w6,v7,v6} |
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vshufps %5, %3, %2, 0x4e ; r = {w3,w4,v1,v3,w7,w8,v8,v5} |
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vsubps %4, %5, %1 ; s = r - q |
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vaddps %1, %5, %1 ; u = r + q |
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vpermilps %1, %1, [perm2] ; k = {u1,u2,u3,u4,u6,u5,u7,u8} |
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vshufps %5, %4, %1, 0xbb |
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vshufps %3, %4, %1, 0xee |
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vperm2f128 %3, %3, %5, 0x13 |
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vxorps %4, %4, [ps_m1m1p1m1p1m1m1m1] ; s *= {1,1,-1,-1,1,-1,-1,-1} |
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vshufps %2, %1, %4, 0xdd |
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vshufps %1, %1, %4, 0x88 |
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vperm2f128 %4, %2, %1, 0x02 ; v = {k1,k3,s1,s3,k2,k4,s2,s4} |
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vperm2f128 %1, %1, %2, 0x13 ; w = {k6,k8,s6,s8,k5,k7,s5,s7} |
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vsubps %5, %1, %3 |
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vblendps %1, %5, %1, 0x55 ; w -= {0,s7,0,k7,0,s8,0,k8} |
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vsubps %2, %4, %1 ; %2 = v - w |
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vaddps %1, %4, %1 ; %1 = v + w |
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%endmacro |
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; In SSE mode do one fft4 transforms |
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; in: %1={r0,i0,r2,i2} %2={r1,i1,r3,i3} |
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; in: %1={r0,i0,r2,i2} %2={r1,i1,r3,i3} |
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; out: %1={r0,r1,r2,r3} %2={i0,i1,i2,i3} |
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; out: %1={r0,r1,r2,r3} %2={i0,i1,i2,i3} |
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; |
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; In AVX mode do two fft4 transforms |
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; in: %1={r0,i0,r2,i2,r4,i4,r6,i6} %2={r1,i1,r3,i3,r5,i5,r7,i7} |
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; out: %1={r0,r1,r2,r3,r4,r5,r6,r7} %2={i0,i1,i2,i3,i4,i5,i6,i7} |
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%macro T4_SSE 3 |
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%macro T4_SSE 3 |
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mova %3, %1 |
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subps %3, %1, %2 ; {t3,t4,-t8,t7} |
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addps %1, %2 ; {t1,t2,t6,t5} |
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addps %1, %1, %2 ; {t1,t2,t6,t5} |
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subps %3, %2 ; {t3,t4,-t8,t7} |
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xorps %3, %3, [ps_p1p1m1p1] |
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xorps %3, [ps_p1p1m1p1] |
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shufps %2, %1, %3, 0xbe ; {t6,t5,t7,t8} |
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mova %2, %1 |
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shufps %1, %1, %3, 0x44 ; {t1,t2,t3,t4} |
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shufps %1, %3, 0x44 ; {t1,t2,t3,t4} |
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subps %3, %1, %2 ; {r2,i2,r3,i3} |
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shufps %2, %3, 0xbe ; {t6,t5,t7,t8} |
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addps %1, %1, %2 ; {r0,i0,r1,i1} |
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mova %3, %1 |
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shufps %2, %1, %3, 0xdd ; {i0,i1,i2,i3} |
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addps %1, %2 ; {r0,i0,r1,i1} |
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shufps %1, %1, %3, 0x88 ; {r0,r1,r2,r3} |
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subps %3, %2 ; {r2,i2,r3,i3} |
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mova %2, %1 |
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shufps %1, %3, 0x88 ; {r0,r1,r2,r3} |
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shufps %2, %3, 0xdd ; {i0,i1,i2,i3} |
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%endmacro |
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%endmacro |
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; In SSE mode do one FFT8 |
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; in: %1={r0,r1,r2,r3} %2={i0,i1,i2,i3} %3={r4,i4,r6,i6} %4={r5,i5,r7,i7} |
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; in: %1={r0,r1,r2,r3} %2={i0,i1,i2,i3} %3={r4,i4,r6,i6} %4={r5,i5,r7,i7} |
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; out: %1={r0,r1,r2,r3} %2={i0,i1,i2,i3} %1={r4,r5,r6,r7} %2={i4,i5,i6,i7} |
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; out: %1={r0,r1,r2,r3} %2={i0,i1,i2,i3} %1={r4,r5,r6,r7} %2={i4,i5,i6,i7} |
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; |
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; In AVX mode do two FFT8 |
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; in: %1={r0,i0,r2,i2,r8, i8, r10,i10} %2={r1,i1,r3,i3,r9, i9, r11,i11} |
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; %3={r4,i4,r6,i6,r12,i12,r14,i14} %4={r5,i5,r7,i7,r13,i13,r15,i15} |
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; out: %1={r0,r1,r2,r3,r8, r9, r10,r11} %2={i0,i1,i2,i3,i8, i9, i10,i11} |
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; %3={r4,r5,r6,r7,r12,r13,r14,r15} %4={i4,i5,i6,i7,i12,i13,i14,i15} |
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%macro T8_SSE 6 |
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%macro T8_SSE 6 |
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mova %6, %3 |
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addps %6, %3, %4 ; {t1,t2,t3,t4} |
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subps %3, %4 ; {r5,i5,r7,i7} |
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subps %3, %3, %4 ; {r5,i5,r7,i7} |
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addps %6, %4 ; {t1,t2,t3,t4} |
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shufps %4, %3, %3, 0xb1 ; {i5,r5,i7,r7} |
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mova %4, %3 |
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mulps %3, %3, [ps_root2mppm] ; {-r5,i5,r7,-i7} |
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shufps %4, %4, 0xb1 ; {i5,r5,i7,r7} |
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mulps %4, %4, [ps_root2] |
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mulps %3, [ps_root2mppm] ; {-r5,i5,r7,-i7} |
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addps %3, %3, %4 ; {t8,t7,ta,t9} |
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mulps %4, [ps_root2] |
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shufps %4, %6, %3, 0x9c ; {t1,t4,t7,ta} |
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addps %3, %4 ; {t8,t7,ta,t9} |
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shufps %6, %6, %3, 0x36 ; {t3,t2,t9,t8} |
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mova %4, %6 |
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subps %3, %6, %4 ; {t6,t5,tc,tb} |
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shufps %6, %3, 0x36 ; {t3,t2,t9,t8} |
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addps %6, %6, %4 ; {t1,t2,t9,ta} |
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shufps %4, %3, 0x9c ; {t1,t4,t7,ta} |
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shufps %5, %6, %3, 0x8d ; {t2,ta,t6,tc} |
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mova %3, %6 |
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shufps %6, %6, %3, 0xd8 ; {t1,t9,t5,tb} |
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addps %6, %4 ; {t1,t2,t9,ta} |
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subps %3, %1, %6 ; {r4,r5,r6,r7} |
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subps %3, %4 ; {t6,t5,tc,tb} |
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addps %1, %1, %6 ; {r0,r1,r2,r3} |
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mova %4, %6 |
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subps %4, %2, %5 ; {i4,i5,i6,i7} |
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shufps %6, %3, 0xd8 ; {t1,t9,t5,tb} |
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addps %2, %2, %5 ; {i0,i1,i2,i3} |
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shufps %4, %3, 0x8d ; {t2,ta,t6,tc} |
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mova %3, %1 |
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mova %5, %2 |
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addps %1, %6 ; {r0,r1,r2,r3} |
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addps %2, %4 ; {i0,i1,i2,i3} |
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subps %3, %6 ; {r4,r5,r6,r7} |
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subps %5, %4 ; {i4,i5,i6,i7} |
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SWAP %4, %5 |
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%endmacro |
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%endmacro |
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; scheduled for cpu-bound sizes |
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; scheduled for cpu-bound sizes |
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@ -148,52 +190,44 @@ section .text align=16 |
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IF%1 mova m4, Z(4) |
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IF%1 mova m4, Z(4) |
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IF%1 mova m5, Z(5) |
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IF%1 mova m5, Z(5) |
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mova m0, %2 ; wre |
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mova m0, %2 ; wre |
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mova m2, m4 |
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mova m1, %3 ; wim |
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mova m1, %3 ; wim |
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mova m3, m5 |
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mulps m2, m4, m0 ; r2*wre |
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mulps m2, m0 ; r2*wre |
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IF%1 mova m6, Z2(6) |
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IF%1 mova m6, Z2(6) |
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mulps m3, m1 ; i2*wim |
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mulps m3, m5, m1 ; i2*wim |
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IF%1 mova m7, Z2(7) |
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IF%1 mova m7, Z2(7) |
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mulps m4, m1 ; r2*wim |
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mulps m4, m4, m1 ; r2*wim |
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mulps m5, m0 ; i2*wre |
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mulps m5, m5, m0 ; i2*wre |
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addps m2, m3 ; r2*wre + i2*wim |
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addps m2, m2, m3 ; r2*wre + i2*wim |
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mova m3, m1 |
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mulps m3, m1, m7 ; i3*wim |
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mulps m1, m6 ; r3*wim |
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subps m5, m5, m4 ; i2*wre - r2*wim |
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subps m5, m4 ; i2*wre - r2*wim |
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mulps m1, m1, m6 ; r3*wim |
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mova m4, m0 |
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mulps m4, m0, m6 ; r3*wre |
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mulps m3, m7 ; i3*wim |
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mulps m0, m0, m7 ; i3*wre |
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mulps m4, m6 ; r3*wre |
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subps m4, m4, m3 ; r3*wre - i3*wim |
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mulps m0, m7 ; i3*wre |
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subps m4, m3 ; r3*wre - i3*wim |
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mova m3, Z(0) |
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mova m3, Z(0) |
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addps m0, m1 ; i3*wre + r3*wim |
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addps m0, m0, m1 ; i3*wre + r3*wim |
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mova m1, m4 |
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subps m1, m4, m2 ; t3 |
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addps m4, m2 ; t5 |
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addps m4, m4, m2 ; t5 |
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subps m1, m2 ; t3 |
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subps m3, m3, m4 ; r2 |
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subps m3, m4 ; r2 |
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addps m4, m4, Z(0) ; r0 |
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addps m4, Z(0) ; r0 |
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mova m6, Z(2) |
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mova m6, Z(2) |
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mova Z(4), m3 |
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mova Z(4), m3 |
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mova Z(0), m4 |
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mova Z(0), m4 |
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mova m3, m5 |
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subps m3, m5, m0 ; t4 |
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subps m5, m0 ; t4 |
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subps m4, m6, m3 ; r3 |
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mova m4, m6 |
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addps m3, m3, m6 ; r1 |
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subps m6, m5 ; r3 |
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mova Z2(6), m4 |
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addps m5, m4 ; r1 |
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mova Z(2), m3 |
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mova Z2(6), m6 |
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mova Z(2), m5 |
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mova m2, Z(3) |
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mova m2, Z(3) |
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addps m3, m0 ; t6 |
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addps m3, m5, m0 ; t6 |
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subps m2, m1 ; i3 |
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subps m2, m2, m1 ; i3 |
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mova m7, Z(1) |
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mova m7, Z(1) |
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addps m1, Z(3) ; i1 |
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addps m1, m1, Z(3) ; i1 |
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mova Z2(7), m2 |
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mova Z2(7), m2 |
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mova Z(3), m1 |
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mova Z(3), m1 |
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mova m4, m7 |
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subps m4, m7, m3 ; i2 |
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subps m7, m3 ; i2 |
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addps m3, m3, m7 ; i0 |
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addps m3, m4 ; i0 |
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mova Z(5), m4 |
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mova Z(5), m7 |
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mova Z(1), m3 |
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mova Z(1), m3 |
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%endmacro |
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%endmacro |
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@ -201,77 +235,55 @@ IF%1 mova m7, Z2(7) |
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%macro PASS_BIG 1 ; (!interleave) |
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%macro PASS_BIG 1 ; (!interleave) |
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mova m4, Z(4) ; r2 |
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mova m4, Z(4) ; r2 |
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mova m5, Z(5) ; i2 |
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mova m5, Z(5) ; i2 |
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mova m2, m4 |
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mova m0, [wq] ; wre |
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mova m0, [wq] ; wre |
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mova m3, m5 |
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mova m1, [wq+o1q] ; wim |
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mova m1, [wq+o1q] ; wim |
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mulps m2, m0 ; r2*wre |
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mulps m2, m4, m0 ; r2*wre |
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mova m6, Z2(6) ; r3 |
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mova m6, Z2(6) ; r3 |
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mulps m3, m1 ; i2*wim |
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mulps m3, m5, m1 ; i2*wim |
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mova m7, Z2(7) ; i3 |
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mova m7, Z2(7) ; i3 |
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mulps m4, m1 ; r2*wim |
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mulps m4, m4, m1 ; r2*wim |
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mulps m5, m0 ; i2*wre |
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mulps m5, m5, m0 ; i2*wre |
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addps m2, m3 ; r2*wre + i2*wim |
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addps m2, m2, m3 ; r2*wre + i2*wim |
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mova m3, m1 |
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mulps m3, m1, m7 ; i3*wim |
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mulps m1, m6 ; r3*wim |
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mulps m1, m1, m6 ; r3*wim |
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subps m5, m4 ; i2*wre - r2*wim |
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subps m5, m5, m4 ; i2*wre - r2*wim |
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mova m4, m0 |
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mulps m4, m0, m6 ; r3*wre |
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mulps m3, m7 ; i3*wim |
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mulps m0, m0, m7 ; i3*wre |
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mulps m4, m6 ; r3*wre |
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subps m4, m4, m3 ; r3*wre - i3*wim |
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mulps m0, m7 ; i3*wre |
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subps m4, m3 ; r3*wre - i3*wim |
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mova m3, Z(0) |
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mova m3, Z(0) |
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addps m0, m1 ; i3*wre + r3*wim |
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addps m0, m0, m1 ; i3*wre + r3*wim |
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mova m1, m4 |
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subps m1, m4, m2 ; t3 |
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addps m4, m2 ; t5 |
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addps m4, m4, m2 ; t5 |
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subps m1, m2 ; t3 |
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subps m3, m3, m4 ; r2 |
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subps m3, m4 ; r2 |
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addps m4, m4, Z(0) ; r0 |
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addps m4, Z(0) ; r0 |
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mova m6, Z(2) |
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mova m6, Z(2) |
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mova Z(4), m3 |
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mova Z(4), m3 |
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mova Z(0), m4 |
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mova Z(0), m4 |
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mova m3, m5 |
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subps m3, m5, m0 ; t4 |
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subps m5, m0 ; t4 |
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subps m4, m6, m3 ; r3 |
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mova m4, m6 |
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addps m3, m3, m6 ; r1 |
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subps m6, m5 ; r3 |
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IF%1 mova Z2(6), m4 |
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addps m5, m4 ; r1 |
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IF%1 mova Z(2), m3 |
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IF%1 mova Z2(6), m6 |
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IF%1 mova Z(2), m5 |
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mova m2, Z(3) |
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mova m2, Z(3) |
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addps m3, m0 ; t6 |
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addps m5, m5, m0 ; t6 |
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subps m2, m1 ; i3 |
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subps m2, m2, m1 ; i3 |
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mova m7, Z(1) |
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mova m7, Z(1) |
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addps m1, Z(3) ; i1 |
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addps m1, m1, Z(3) ; i1 |
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IF%1 mova Z2(7), m2 |
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IF%1 mova Z2(7), m2 |
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IF%1 mova Z(3), m1 |
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IF%1 mova Z(3), m1 |
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mova m4, m7 |
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subps m6, m7, m5 ; i2 |
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subps m7, m3 ; i2 |
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addps m5, m5, m7 ; i0 |
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addps m3, m4 ; i0 |
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IF%1 mova Z(5), m6 |
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IF%1 mova Z(5), m7 |
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IF%1 mova Z(1), m5 |
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IF%1 mova Z(1), m3 |
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%if %1==0 |
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%if %1==0 |
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mova m4, m5 ; r1 |
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INTERL m1, m3, m7, Z, 2 |
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mova m0, m6 ; r3 |
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INTERL m2, m4, m0, Z2, 6 |
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unpcklps m5, m1 |
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unpckhps m4, m1 |
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unpcklps m6, m2 |
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unpckhps m0, m2 |
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mova m1, Z(0) |
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mova m1, Z(0) |
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mova m2, Z(4) |
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mova m2, Z(4) |
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mova Z(2), m5 |
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mova Z(3), m4 |
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INTERL m5, m1, m3, Z, 0 |
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mova Z2(6), m6 |
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INTERL m6, m2, m7, Z, 4 |
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mova Z2(7), m0 |
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mova m5, m1 ; r0 |
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mova m4, m2 ; r2 |
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unpcklps m1, m3 |
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unpckhps m5, m3 |
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unpcklps m2, m7 |
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unpckhps m4, m7 |
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mova Z(0), m1 |
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mova Z(1), m5 |
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mova Z(4), m2 |
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mova Z(5), m4 |
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%endif |
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%endif |
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%endmacro |
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%endmacro |
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@ -281,13 +293,106 @@ IF%1 mova Z(1), m3 |
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punpckhdq %3, %2 |
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punpckhdq %3, %2 |
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%endmacro |
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%endmacro |
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INIT_XMM |
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%define mova movaps |
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%define Z(x) [r0+mmsize*x] |
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%define Z(x) [r0+mmsize*x] |
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%define Z2(x) [r0+mmsize*x] |
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%define Z2(x) [r0+mmsize*x] |
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%define ZH(x) [r0+mmsize*x+mmsize/2] |
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INIT_YMM |
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align 16 |
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fft8_avx: |
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mova m0, Z(0) |
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mova m1, Z(1) |
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T8_AVX m0, m1, m2, m3, m4 |
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mova Z(0), m0 |
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mova Z(1), m1 |
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ret |
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align 16 |
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fft16_avx: |
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mova m2, Z(2) |
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mova m3, Z(3) |
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T4_SSE m2, m3, m7 |
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mova m0, Z(0) |
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mova m1, Z(1) |
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T8_AVX m0, m1, m4, m5, m7 |
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mova m4, [ps_cos16_1] |
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mova m5, [ps_cos16_2] |
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vmulps m6, m2, m4 |
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vmulps m7, m3, m5 |
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vaddps m7, m7, m6 |
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vmulps m2, m2, m5 |
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vmulps m3, m3, m4 |
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vsubps m3, m3, m2 |
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vblendps m2, m7, m3, 0xf0 |
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vperm2f128 m3, m7, m3, 0x21 |
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vaddps m4, m2, m3 |
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vsubps m2, m3, m2 |
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vperm2f128 m2, m2, m2, 0x01 |
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vsubps m3, m1, m2 |
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vaddps m1, m1, m2 |
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vsubps m5, m0, m4 |
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vaddps m0, m0, m4 |
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vextractf128 Z(0), m0, 0 |
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vextractf128 ZH(0), m1, 0 |
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vextractf128 Z(1), m0, 1 |
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vextractf128 ZH(1), m1, 1 |
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vextractf128 Z(2), m5, 0 |
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vextractf128 ZH(2), m3, 0 |
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vextractf128 Z(3), m5, 1 |
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vextractf128 ZH(3), m3, 1 |
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ret |
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align 16 |
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fft32_avx: |
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call fft16_avx |
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mova m0, Z(4) |
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mova m1, Z(5) |
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T4_SSE m0, m1, m4 |
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mova m2, Z(6) |
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mova m3, Z(7) |
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T8_SSE m0, m1, m2, m3, m4, m6 |
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; m0={r0,r1,r2,r3,r8, r9, r10,r11} m1={i0,i1,i2,i3,i8, i9, i10,i11} |
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; m2={r4,r5,r6,r7,r12,r13,r14,r15} m3={i4,i5,i6,i7,i12,i13,i14,i15} |
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vperm2f128 m4, m0, m2, 0x20 |
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vperm2f128 m5, m1, m3, 0x20 |
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vperm2f128 m6, m0, m2, 0x31 |
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vperm2f128 m7, m1, m3, 0x31 |
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PASS_SMALL 0, [cos_32], [cos_32+32] |
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ret |
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fft32_interleave_avx: |
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call fft32_avx |
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mov r2d, 32 |
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.deint_loop: |
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mova m2, Z(0) |
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mova m3, Z(1) |
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vunpcklps m0, m2, m3 |
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vunpckhps m1, m2, m3 |
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vextractf128 Z(0), m0, 0 |
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vextractf128 ZH(0), m1, 0 |
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vextractf128 Z(1), m0, 1 |
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vextractf128 ZH(1), m1, 1 |
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add r0, mmsize*2 |
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sub r2d, mmsize/4 |
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jg .deint_loop |
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ret |
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INIT_XMM |
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%define movdqa movaps |
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align 16 |
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align 16 |
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fft4_avx: |
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fft4_sse: |
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fft4_sse: |
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mova m0, Z(0) |
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mova m0, Z(0) |
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mova m1, Z(1) |
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mova m1, Z(1) |
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@ -406,6 +511,8 @@ FFT48_3DN _3dn |
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%define Z(x) [zq + o1q*(x&6) + mmsize*(x&1)] |
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%define Z(x) [zq + o1q*(x&6) + mmsize*(x&1)] |
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%define Z2(x) [zq + o3q + mmsize*(x&1)] |
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%define Z2(x) [zq + o3q + mmsize*(x&1)] |
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%define ZH(x) [zq + o1q*(x&6) + mmsize*(x&1) + mmsize/2] |
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%define Z2H(x) [zq + o3q + mmsize*(x&1) + mmsize/2] |
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%macro DECL_PASS 2+ ; name, payload |
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%macro DECL_PASS 2+ ; name, payload |
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align 16 |
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align 16 |
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@ -423,8 +530,34 @@ DEFINE_ARGS z, w, n, o1, o3 |
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rep ret |
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rep ret |
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%endmacro |
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%endmacro |
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INIT_YMM |
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%macro INTERL_AVX 5 |
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vunpckhps %3, %2, %1 |
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vunpcklps %2, %2, %1 |
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vextractf128 %4(%5), %2, 0 |
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vextractf128 %4 %+ H(%5), %3, 0 |
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vextractf128 %4(%5 + 1), %2, 1 |
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vextractf128 %4 %+ H(%5 + 1), %3, 1 |
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%endmacro |
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%define INTERL INTERL_AVX |
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DECL_PASS pass_avx, PASS_BIG 1 |
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DECL_PASS pass_interleave_avx, PASS_BIG 0 |
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INIT_XMM |
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INIT_XMM |
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%define mova movaps |
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%macro INTERL_SSE 5 |
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mova %3, %2 |
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unpcklps %2, %1 |
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unpckhps %3, %1 |
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mova %4(%5), %2 |
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mova %4(%5+1), %3 |
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%endmacro |
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%define INTERL INTERL_SSE |
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DECL_PASS pass_sse, PASS_BIG 1 |
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DECL_PASS pass_sse, PASS_BIG 1 |
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DECL_PASS pass_interleave_sse, PASS_BIG 0 |
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DECL_PASS pass_interleave_sse, PASS_BIG 0 |
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@ -457,9 +590,12 @@ DECL_PASS pass_interleave_3dn, PASS_BIG 0 |
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%macro DECL_FFT 2-3 ; nbits, cpu, suffix |
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%macro DECL_FFT 2-3 ; nbits, cpu, suffix |
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%xdefine list_of_fft fft4%2 SECTION_REL, fft8%2 SECTION_REL |
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%xdefine list_of_fft fft4%2 SECTION_REL, fft8%2 SECTION_REL |
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%if %1==5 |
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%if %1>=5 |
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%xdefine list_of_fft list_of_fft, fft16%2 SECTION_REL |
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%xdefine list_of_fft list_of_fft, fft16%2 SECTION_REL |
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%endif |
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%endif |
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%if %1>=6 |
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%xdefine list_of_fft list_of_fft, fft32%3%2 SECTION_REL |
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%endif |
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%assign n 1<<%1 |
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%assign n 1<<%1 |
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%rep 17-%1 |
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%rep 17-%1 |
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@ -492,9 +628,14 @@ section .text |
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; The others pass args in registers and don't spill anything. |
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; The others pass args in registers and don't spill anything. |
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cglobal fft_dispatch%3%2, 2,5,8, z, nbits |
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cglobal fft_dispatch%3%2, 2,5,8, z, nbits |
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FFT_DISPATCH %3%2, nbits |
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FFT_DISPATCH %3%2, nbits |
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%ifidn %2, _avx |
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vzeroupper |
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%endif |
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RET |
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RET |
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%endmacro ; DECL_FFT |
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%endmacro ; DECL_FFT |
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DECL_FFT 6, _avx |
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DECL_FFT 6, _avx, _interleave |
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DECL_FFT 5, _sse |
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DECL_FFT 5, _sse |
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DECL_FFT 5, _sse, _interleave |
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DECL_FFT 5, _sse, _interleave |
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DECL_FFT 4, _3dn |
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DECL_FFT 4, _3dn |
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@ -533,21 +674,53 @@ INIT_XMM |
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%endmacro |
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%endmacro |
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%macro CMUL 6 ;j, xmm0, xmm1, 3, 4, 5 |
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%macro CMUL 6 ;j, xmm0, xmm1, 3, 4, 5 |
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movaps xmm6, [%4+%1*2] |
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mulps m6, %3, [%5+%1] |
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movaps %2, [%4+%1*2+0x10] |
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mulps m7, %2, [%5+%1] |
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movaps %3, xmm6 |
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mulps %2, %2, [%6+%1] |
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movaps xmm7, %2 |
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mulps %3, %3, [%6+%1] |
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mulps xmm6, [%5+%1] |
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subps %2, %2, m6 |
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mulps %2, [%6+%1] |
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addps %3, %3, m7 |
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mulps %3, [%6+%1] |
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%endmacro |
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mulps xmm7, [%5+%1] |
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subps %2, xmm6 |
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%macro POSROTATESHUF_AVX 5 ;j, k, z+n8, tcos+n8, tsin+n8 |
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addps %3, xmm7 |
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.post: |
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vmovaps ymm1, [%3+%1*2] |
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vmovaps ymm0, [%3+%1*2+0x20] |
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vmovaps ymm3, [%3+%2*2] |
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vmovaps ymm2, [%3+%2*2+0x20] |
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CMUL %1, ymm0, ymm1, %3, %4, %5 |
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CMUL %2, ymm2, ymm3, %3, %4, %5 |
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vshufps ymm1, ymm1, ymm1, 0x1b |
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vshufps ymm3, ymm3, ymm3, 0x1b |
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vperm2f128 ymm1, ymm1, ymm1, 0x01 |
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vperm2f128 ymm3, ymm3, ymm3, 0x01 |
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vunpcklps ymm6, ymm2, ymm1 |
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vunpckhps ymm4, ymm2, ymm1 |
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vunpcklps ymm7, ymm0, ymm3 |
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vunpckhps ymm5, ymm0, ymm3 |
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vextractf128 [%3+%1*2], ymm7, 0 |
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vextractf128 [%3+%1*2+0x10], ymm5, 0 |
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vextractf128 [%3+%1*2+0x20], ymm7, 1 |
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vextractf128 [%3+%1*2+0x30], ymm5, 1 |
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vextractf128 [%3+%2*2], ymm6, 0 |
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vextractf128 [%3+%2*2+0x10], ymm4, 0 |
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vextractf128 [%3+%2*2+0x20], ymm6, 1 |
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vextractf128 [%3+%2*2+0x30], ymm4, 1 |
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sub %2, 0x20 |
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add %1, 0x20 |
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jl .post |
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%endmacro |
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%endmacro |
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%macro POSROTATESHUF 5 ;j, k, z+n8, tcos+n8, tsin+n8 |
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%macro POSROTATESHUF 5 ;j, k, z+n8, tcos+n8, tsin+n8 |
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.post: |
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.post: |
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movaps xmm1, [%3+%1*2] |
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movaps xmm0, [%3+%1*2+0x10] |
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CMUL %1, xmm0, xmm1, %3, %4, %5 |
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CMUL %1, xmm0, xmm1, %3, %4, %5 |
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movaps xmm5, [%3+%2*2] |
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movaps xmm4, [%3+%2*2+0x10] |
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CMUL %2, xmm4, xmm5, %3, %4, %5 |
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CMUL %2, xmm4, xmm5, %3, %4, %5 |
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shufps xmm1, xmm1, 0x1b |
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shufps xmm1, xmm1, 0x1b |
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shufps xmm5, xmm5, 0x1b |
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shufps xmm5, xmm5, 0x1b |
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@ -566,7 +739,8 @@ INIT_XMM |
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jl .post |
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jl .post |
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%endmacro |
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%endmacro |
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cglobal imdct_half_sse, 3,7,8; FFTContext *s, FFTSample *output, const FFTSample *input |
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%macro DECL_IMDCT 2 |
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cglobal imdct_half%1, 3,7,8; FFTContext *s, FFTSample *output, const FFTSample *input |
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%ifdef ARCH_X86_64 |
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%ifdef ARCH_X86_64 |
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%define rrevtab r10 |
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%define rrevtab r10 |
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%define rtcos r11 |
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%define rtcos r11 |
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@ -641,7 +815,7 @@ cglobal imdct_half_sse, 3,7,8; FFTContext *s, FFTSample *output, const FFTSample |
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mov r0, r1 |
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mov r0, r1 |
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mov r1d, [r5+FFTContext.nbits] |
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mov r1d, [r5+FFTContext.nbits] |
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FFT_DISPATCH _sse, r1 |
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FFT_DISPATCH %1, r1 |
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mov r0d, [r5+FFTContext.mdctsize] |
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mov r0d, [r5+FFTContext.mdctsize] |
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add r6, r0 |
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add r6, r0 |
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@ -653,14 +827,24 @@ cglobal imdct_half_sse, 3,7,8; FFTContext *s, FFTSample *output, const FFTSample |
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mov rtsin, [esp+4] |
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mov rtsin, [esp+4] |
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%endif |
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%endif |
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neg r0 |
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neg r0 |
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mov r1, -16 |
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mov r1, -mmsize |
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sub r1, r0 |
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sub r1, r0 |
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POSROTATESHUF r0, r1, r6, rtcos, rtsin |
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%2 r0, r1, r6, rtcos, rtsin |
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%ifdef ARCH_X86_64 |
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%ifdef ARCH_X86_64 |
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pop r14 |
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pop r14 |
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pop r13 |
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pop r13 |
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pop r12 |
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pop r12 |
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%else |
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%else |
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add esp, 12 |
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add esp, 12 |
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%endif |
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%ifidn avx_enabled, 1 |
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vzeroupper |
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%endif |
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%endif |
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RET |
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RET |
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%endmacro |
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DECL_IMDCT _sse, POSROTATESHUF |
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INIT_YMM |
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DECL_IMDCT _avx, POSROTATESHUF_AVX |
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