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ARM: move VFP DSP functions to dsputils_vfp.S

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Originally committed as revision 15727 to svn://svn.ffmpeg.org/ffmpeg/trunk
pull/126/head
Måns Rullgård 17 years ago
parent a648516b95
commit 83ad74e708
3 changed files with 196 additions and 180 deletions
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  1. 1
      libavcodec/Makefile
  2. 188
      libavcodec/armv4l/dsputil_vfp.S
  3. 187
      libavcodec/armv4l/float_arm_vfp.c

1
libavcodec/Makefile
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@ -433,6 +433,7 @@ OBJS-$(HAVE_ARMV5TE) += armv4l/mpegvideo_armv5te.o \
armv4l/simple_idct_armv5te.o \ armv4l/simple_idct_armv5te.o \
OBJS-$(HAVE_ARMVFP) += armv4l/float_arm_vfp.o \ OBJS-$(HAVE_ARMVFP) += armv4l/float_arm_vfp.o \
armv4l/dsputil_vfp.o \
OBJS-$(HAVE_ARMV6) += armv4l/simple_idct_armv6.o \ OBJS-$(HAVE_ARMV6) += armv4l/simple_idct_armv6.o \

188
libavcodec/armv4l/dsputil_vfp.S
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@ -0,0 +1,188 @@
/*
* Copyright (c) 2008 Siarhei Siamashka <ssvb@users.sourceforge.net>
*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "config.h"
#include "asm.S"
/*
* VFP is a floating point coprocessor used in some ARM cores. VFP11 has 1 cycle
* throughput for almost all the instructions (except for double precision
* arithmetics), but rather high latency. Latency is 4 cycles for loads and 8 cycles
* for arithmetic operations. Scheduling code to avoid pipeline stalls is very
* important for performance. One more interesting feature is that VFP has
* independent load/store and arithmetics pipelines, so it is possible to make
* them work simultaneously and get more than 1 operation per cycle. Load/store
* pipeline can process 2 single precision floating point values per cycle and
* supports bulk loads and stores for large sets of registers. Arithmetic operations
* can be done on vectors, which allows to keep the arithmetics pipeline busy,
* while the processor may issue and execute other instructions. Detailed
* optimization manuals can be found at http://www.arm.com
*/
/**
* ARM VFP optimized implementation of 'vector_fmul_c' function.
* Assume that len is a positive number and is multiple of 8
*/
@ void ff_vector_fmul_vfp(float *dst, const float *src, int len)
function ff_vector_fmul_vfp, export=1
vpush {d8-d15}
mov r3, r0
fmrx r12, fpscr
orr r12, r12, #(3 << 16) /* set vector size to 4 */
fmxr fpscr, r12
fldmias r3!, {s0-s3}
fldmias r1!, {s8-s11}
fldmias r3!, {s4-s7}
fldmias r1!, {s12-s15}
fmuls s8, s0, s8
1:
subs r2, r2, #16
fmuls s12, s4, s12
fldmiasge r3!, {s16-s19}
fldmiasge r1!, {s24-s27}
fldmiasge r3!, {s20-s23}
fldmiasge r1!, {s28-s31}
fmulsge s24, s16, s24
fstmias r0!, {s8-s11}
fstmias r0!, {s12-s15}
fmulsge s28, s20, s28
fldmiasgt r3!, {s0-s3}
fldmiasgt r1!, {s8-s11}
fldmiasgt r3!, {s4-s7}
fldmiasgt r1!, {s12-s15}
fmulsge s8, s0, s8
fstmiasge r0!, {s24-s27}
fstmiasge r0!, {s28-s31}
bgt 1b
bic r12, r12, #(7 << 16) /* set vector size back to 1 */
fmxr fpscr, r12
vpop {d8-d15}
bx lr
.endfunc
/**
* ARM VFP optimized implementation of 'vector_fmul_reverse_c' function.
* Assume that len is a positive number and is multiple of 8
*/
@ void ff_vector_fmul_reverse_vfp(float *dst, const float *src0,
@ const float *src1, int len)
function ff_vector_fmul_reverse_vfp, export=1
vpush {d8-d15}
add r2, r2, r3, lsl #2
fldmdbs r2!, {s0-s3}
fldmias r1!, {s8-s11}
fldmdbs r2!, {s4-s7}
fldmias r1!, {s12-s15}
fmuls s8, s3, s8
fmuls s9, s2, s9
fmuls s10, s1, s10
fmuls s11, s0, s11
1:
subs r3, r3, #16
fldmdbsge r2!, {s16-s19}
fmuls s12, s7, s12
fldmiasge r1!, {s24-s27}
fmuls s13, s6, s13
fldmdbsge r2!, {s20-s23}
fmuls s14, s5, s14
fldmiasge r1!, {s28-s31}
fmuls s15, s4, s15
fmulsge s24, s19, s24
fldmdbsgt r2!, {s0-s3}
fmulsge s25, s18, s25
fstmias r0!, {s8-s13}
fmulsge s26, s17, s26
fldmiasgt r1!, {s8-s11}
fmulsge s27, s16, s27
fmulsge s28, s23, s28
fldmdbsgt r2!, {s4-s7}
fmulsge s29, s22, s29
fstmias r0!, {s14-s15}
fmulsge s30, s21, s30
fmulsge s31, s20, s31
fmulsge s8, s3, s8
fldmiasgt r1!, {s12-s15}
fmulsge s9, s2, s9
fmulsge s10, s1, s10
fstmiasge r0!, {s24-s27}
fmulsge s11, s0, s11
fstmiasge r0!, {s28-s31}
bgt 1b
vpop {d8-d15}
bx lr
.endfunc
#ifdef HAVE_ARMV6
/**
* ARM VFP optimized float to int16 conversion.
* Assume that len is a positive number and is multiple of 8, destination
* buffer is at least 4 bytes aligned (8 bytes alignment is better for
* performance), little endian byte sex
*/
@ void ff_float_to_int16_vfp(int16_t *dst, const float *src, int len)
function ff_float_to_int16_vfp, export=1
push {r4-r8,lr}
vpush {d8-d11}
fldmias r1!, {s16-s23}
ftosis s0, s16
ftosis s1, s17
ftosis s2, s18
ftosis s3, s19
ftosis s4, s20
ftosis s5, s21
ftosis s6, s22
ftosis s7, s23
1:
subs r2, r2, #8
fmrrs r3, r4, {s0, s1}
fmrrs r5, r6, {s2, s3}
fmrrs r7, r8, {s4, s5}
fmrrs ip, lr, {s6, s7}
fldmiasgt r1!, {s16-s23}
ssat r4, #16, r4
ssat r3, #16, r3
ssat r6, #16, r6
ssat r5, #16, r5
pkhbt r3, r3, r4, lsl #16
pkhbt r4, r5, r6, lsl #16
ftosisgt s0, s16
ftosisgt s1, s17
ftosisgt s2, s18
ftosisgt s3, s19
ftosisgt s4, s20
ftosisgt s5, s21
ftosisgt s6, s22
ftosisgt s7, s23
ssat r8, #16, r8
ssat r7, #16, r7
ssat lr, #16, lr
ssat ip, #16, ip
pkhbt r5, r7, r8, lsl #16
pkhbt r6, ip, lr, lsl #16
stmia r0!, {r3-r6}
bgt 1b
vpop {d8-d11}
pop {r4-r8,pc}
.endfunc
#endif

187
libavcodec/armv4l/float_arm_vfp.c
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@ -20,189 +20,16 @@
#include "libavcodec/dsputil.h" #include "libavcodec/dsputil.h"
/* extern void ff_vector_fmul_vfp(float *dst, const float *src, int len);
* VFP is a floating point coprocessor used in some ARM cores. VFP11 has 1 cycle extern void ff_vector_fmul_reverse_vfp(float *dst, const float *src0,
* throughput for almost all the instructions (except for double precision const float *src1, int len);
* arithmetics), but rather high latency. Latency is 4 cycles for loads and 8 cycles extern void ff_float_to_int16_vfp(int16_t *dst, const float *src, long len);
* for arithmetic operations. Scheduling code to avoid pipeline stalls is very
* important for performance. One more interesting feature is that VFP has
* independent load/store and arithmetics pipelines, so it is possible to make
* them work simultaneously and get more than 1 operation per cycle. Load/store
* pipeline can process 2 single precision floating point values per cycle and
* supports bulk loads and stores for large sets of registers. Arithmetic operations
* can be done on vectors, which allows to keep the arithmetics pipeline busy,
* while the processor may issue and execute other instructions. Detailed
* optimization manuals can be found at http://www.arm.com
*/
/**
* ARM VFP optimized implementation of 'vector_fmul_c' function.
* Assume that len is a positive number and is multiple of 8
*/
static void vector_fmul_vfp(float *dst, const float *src, int len)
{
int tmp;
__asm__ volatile(
"fmrx %[tmp], fpscr\n\t"
"orr %[tmp], %[tmp], #(3 << 16)\n\t" /* set vector size to 4 */
"fmxr fpscr, %[tmp]\n\t"
"fldmias %[dst_r]!, {s0-s3}\n\t"
"fldmias %[src]!, {s8-s11}\n\t"
"fldmias %[dst_r]!, {s4-s7}\n\t"
"fldmias %[src]!, {s12-s15}\n\t"
"fmuls s8, s0, s8\n\t"
"1:\n\t"
"subs %[len], %[len], #16\n\t"
"fmuls s12, s4, s12\n\t"
"fldmiasge %[dst_r]!, {s16-s19}\n\t"
"fldmiasge %[src]!, {s24-s27}\n\t"
"fldmiasge %[dst_r]!, {s20-s23}\n\t"
"fldmiasge %[src]!, {s28-s31}\n\t"
"fmulsge s24, s16, s24\n\t"
"fstmias %[dst_w]!, {s8-s11}\n\t"
"fstmias %[dst_w]!, {s12-s15}\n\t"
"fmulsge s28, s20, s28\n\t"
"fldmiasgt %[dst_r]!, {s0-s3}\n\t"
"fldmiasgt %[src]!, {s8-s11}\n\t"
"fldmiasgt %[dst_r]!, {s4-s7}\n\t"
"fldmiasgt %[src]!, {s12-s15}\n\t"
"fmulsge s8, s0, s8\n\t"
"fstmiasge %[dst_w]!, {s24-s27}\n\t"
"fstmiasge %[dst_w]!, {s28-s31}\n\t"
"bgt 1b\n\t"
"bic %[tmp], %[tmp], #(7 << 16)\n\t" /* set vector size back to 1 */
"fmxr fpscr, %[tmp]\n\t"
: [dst_w] "+&r" (dst), [dst_r] "+&r" (dst), [src] "+&r" (src), [len] "+&r" (len), [tmp] "=&r" (tmp)
:
: "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
"s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
"s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
"cc", "memory");
}
/**
* ARM VFP optimized implementation of 'vector_fmul_reverse_c' function.
* Assume that len is a positive number and is multiple of 8
*/
static void vector_fmul_reverse_vfp(float *dst, const float *src0, const float *src1, int len)
{
src1 += len;
__asm__ volatile(
"fldmdbs %[src1]!, {s0-s3}\n\t"
"fldmias %[src0]!, {s8-s11}\n\t"
"fldmdbs %[src1]!, {s4-s7}\n\t"
"fldmias %[src0]!, {s12-s15}\n\t"
"fmuls s8, s3, s8\n\t"
"fmuls s9, s2, s9\n\t"
"fmuls s10, s1, s10\n\t"
"fmuls s11, s0, s11\n\t"
"1:\n\t"
"subs %[len], %[len], #16\n\t"
"fldmdbsge %[src1]!, {s16-s19}\n\t"
"fmuls s12, s7, s12\n\t"
"fldmiasge %[src0]!, {s24-s27}\n\t"
"fmuls s13, s6, s13\n\t"
"fldmdbsge %[src1]!, {s20-s23}\n\t"
"fmuls s14, s5, s14\n\t"
"fldmiasge %[src0]!, {s28-s31}\n\t"
"fmuls s15, s4, s15\n\t"
"fmulsge s24, s19, s24\n\t"
"fldmdbsgt %[src1]!, {s0-s3}\n\t"
"fmulsge s25, s18, s25\n\t"
"fstmias %[dst]!, {s8-s13}\n\t"
"fmulsge s26, s17, s26\n\t"
"fldmiasgt %[src0]!, {s8-s11}\n\t"
"fmulsge s27, s16, s27\n\t"
"fmulsge s28, s23, s28\n\t"
"fldmdbsgt %[src1]!, {s4-s7}\n\t"
"fmulsge s29, s22, s29\n\t"
"fstmias %[dst]!, {s14-s15}\n\t"
"fmulsge s30, s21, s30\n\t"
"fmulsge s31, s20, s31\n\t"
"fmulsge s8, s3, s8\n\t"
"fldmiasgt %[src0]!, {s12-s15}\n\t"
"fmulsge s9, s2, s9\n\t"
"fmulsge s10, s1, s10\n\t"
"fstmiasge %[dst]!, {s24-s27}\n\t"
"fmulsge s11, s0, s11\n\t"
"fstmiasge %[dst]!, {s28-s31}\n\t"
"bgt 1b\n\t"
: [dst] "+&r" (dst), [src0] "+&r" (src0), [src1] "+&r" (src1), [len] "+&r" (len)
:
: "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
"s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
"s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
"cc", "memory");
}
#ifdef HAVE_ARMV6
/**
* ARM VFP optimized float to int16 conversion.
* Assume that len is a positive number and is multiple of 8, destination
* buffer is at least 4 bytes aligned (8 bytes alignment is better for
* performance), little endian byte sex
*/
void float_to_int16_vfp(int16_t *dst, const float *src, int len)
{
__asm__ volatile(
"fldmias %[src]!, {s16-s23}\n\t"
"ftosis s0, s16\n\t"
"ftosis s1, s17\n\t"
"ftosis s2, s18\n\t"
"ftosis s3, s19\n\t"
"ftosis s4, s20\n\t"
"ftosis s5, s21\n\t"
"ftosis s6, s22\n\t"
"ftosis s7, s23\n\t"
"1:\n\t"
"subs %[len], %[len], #8\n\t"
"fmrrs r3, r4, {s0, s1}\n\t"
"fmrrs r5, r6, {s2, s3}\n\t"
"fmrrs r7, r8, {s4, s5}\n\t"
"fmrrs ip, lr, {s6, s7}\n\t"
"fldmiasgt %[src]!, {s16-s23}\n\t"
"ssat r4, #16, r4\n\t"
"ssat r3, #16, r3\n\t"
"ssat r6, #16, r6\n\t"
"ssat r5, #16, r5\n\t"
"pkhbt r3, r3, r4, lsl #16\n\t"
"pkhbt r4, r5, r6, lsl #16\n\t"
"ftosisgt s0, s16\n\t"
"ftosisgt s1, s17\n\t"
"ftosisgt s2, s18\n\t"
"ftosisgt s3, s19\n\t"
"ftosisgt s4, s20\n\t"
"ftosisgt s5, s21\n\t"
"ftosisgt s6, s22\n\t"
"ftosisgt s7, s23\n\t"
"ssat r8, #16, r8\n\t"
"ssat r7, #16, r7\n\t"
"ssat lr, #16, lr\n\t"
"ssat ip, #16, ip\n\t"
"pkhbt r5, r7, r8, lsl #16\n\t"
"pkhbt r6, ip, lr, lsl #16\n\t"
"stmia %[dst]!, {r3-r6}\n\t"
"bgt 1b\n\t"
: [dst] "+&r" (dst), [src] "+&r" (src), [len] "+&r" (len)
:
: "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
"s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
"r3", "r4", "r5", "r6", "r7", "r8", "ip", "lr",
"cc", "memory");
}
#endif
void ff_float_init_arm_vfp(DSPContext* c, AVCodecContext *avctx) void ff_float_init_arm_vfp(DSPContext* c, AVCodecContext *avctx)
{ {
c->vector_fmul = vector_fmul_vfp; c->vector_fmul = ff_vector_fmul_vfp;
c->vector_fmul_reverse = vector_fmul_reverse_vfp; c->vector_fmul_reverse = ff_vector_fmul_reverse_vfp;
#ifdef HAVE_ARMV6 #ifdef HAVE_ARMV6
c->float_to_int16 = float_to_int16_vfp; c->float_to_int16 = ff_float_to_int16_vfp;
#endif #endif
} }

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