From 529d4230123dbb33a719a4d5ec7e47567f04cd06 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?R=C3=A9mi=20Denis-Courmont?= <remi@remlab.net>
Date: Mon, 22 Jul 2024 20:24:30 +0300
Subject: [PATCH] lavu/riscv: remove bespoke SH{1,2,3}ADD assembler

configure checks that the assembler supports the B extension (or rather
its constituents) anyway. These macros were dodging sanity checks for
unsupported instructions and nothing else.
---
 libavutil/riscv/asm.S | 19 -------------------
 1 file changed, 19 deletions(-)

diff --git a/libavutil/riscv/asm.S b/libavutil/riscv/asm.S
index 0c29680d84..8b96e07b75 100644
--- a/libavutil/riscv/asm.S
+++ b/libavutil/riscv/asm.S
@@ -83,25 +83,6 @@
             .endm
         .endm
 
-#if !defined (__riscv_zba)
-        /* SH{1,2,3}ADD definitions for pre-Zba assemblers */
-        .macro  shnadd n, rd, rs1, rs2
-        .insn r OP, 2 * \n, 16, \rd, \rs1, \rs2
-        .endm
-
-        .macro  sh1add rd, rs1, rs2
-        shnadd  1, \rd, \rs1, \rs2
-        .endm
-
-        .macro  sh2add rd, rs1, rs2
-        shnadd  2, \rd, \rs1, \rs2
-        .endm
-
-        .macro  sh3add rd, rs1, rs2
-        shnadd  3, \rd, \rs1, \rs2
-        .endm
-#endif
-
 #if defined (__riscv_v_elen)
 # define RV_V_ELEN __riscv_v_elen
 #else