mirror of https://github.com/FFmpeg/FFmpeg.git
* commit 'b4dd424d96f09f9bafb88e47f37df65dc4529143': Remove all SPARC architecture optimizations Conflicts: Makefile configure libavcodec/sparc/dsputil_vis.c libavcodec/sparc/dsputil_vis.h libavcodec/sparc/hpeldsp_vis.c libavcodec/sparc/simple_idct_vis.c libavcodec/sparc/vis.h libswscale/sparc/yuv2rgb_vis.c libswscale/swscale_internal.h If someone wants to maintain these (or other) SPARC optimizations, please contact me or ffmpeg-devel. I am happy to revert this removial if theres someone considering to maintain this code. Merged-by: Michael Niedermayer <michaelni@gmx.at>pull/293/head
Michael Niedermayer
11 years ago
commit
3fc2362aef
20 changed files with 6 additions and 4643 deletions
@ -1,4 +0,0 @@ |
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VIS-OBJS += sparc/dsputil_vis.o \
|
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sparc/simple_idct_vis.o \
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|
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VIS-OBJS-$(CONFIG_HPELDSP) += sparc/hpeldsp_vis.o
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@ -1,40 +0,0 @@ |
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/*
|
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* Copyright (C) 2003 David S. Miller <davem@redhat.com> |
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* |
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* This file is part of FFmpeg. |
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* |
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* FFmpeg is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU Lesser General Public |
||||
* License as published by the Free Software Foundation; either |
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* version 2.1 of the License, or (at your option) any later version. |
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* |
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* FFmpeg is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
||||
* Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public |
||||
* License along with FFmpeg; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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*/ |
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|
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#include "libavutil/attributes.h" |
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#include "libavcodec/dsputil.h" |
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#include "dsputil_vis.h" |
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#include "vis.h" |
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|
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av_cold void ff_dsputil_init_vis(DSPContext *c, AVCodecContext *avctx) |
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{ |
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/* VIS-specific optimizations */ |
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int accel = vis_level (); |
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const int high_bit_depth = avctx->bits_per_raw_sample > 8; |
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|
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if (accel & ACCEL_SPARC_VIS && !high_bit_depth) { |
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if (avctx->idct_algo == FF_IDCT_SIMPLEVIS) { |
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c->idct_put = ff_simple_idct_put_vis; |
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c->idct_add = ff_simple_idct_add_vis; |
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c->idct = ff_simple_idct_vis; |
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c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM; |
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} |
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} |
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} |
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@ -1,28 +0,0 @@ |
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/*
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* This file is part of FFmpeg. |
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* |
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* FFmpeg is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU Lesser General Public |
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* License as published by the Free Software Foundation; either |
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* version 2.1 of the License, or (at your option) any later version. |
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* |
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* FFmpeg is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public |
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* License along with FFmpeg; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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*/ |
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|
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#ifndef AVCODEC_SPARC_DSPUTIL_VIS_H |
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#define AVCODEC_SPARC_DSPUTIL_VIS_H |
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#include <stdint.h> |
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void ff_simple_idct_put_vis(uint8_t *dest, int line_size, int16_t *data); |
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void ff_simple_idct_add_vis(uint8_t *dest, int line_size, int16_t *data); |
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void ff_simple_idct_vis(int16_t *data); |
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#endif /* AVCODEC_SPARC_DSPUTIL_VIS_H */ |
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File diff suppressed because it is too large
Load Diff
@ -1,531 +0,0 @@ |
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/*
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* SPARC VIS optimized inverse DCT |
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* Copyright (c) 2007 Denes Balatoni < dbalatoni XatX interware XdotX hu > |
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* |
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* I did consult the following fine web page about dct |
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* http://www.geocities.com/ssavekar/dct.htm
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* |
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* This file is part of FFmpeg. |
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* |
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* FFmpeg is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU Lesser General Public |
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* License as published by the Free Software Foundation; either |
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* version 2.1 of the License, or (at your option) any later version. |
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* |
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* FFmpeg is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* Lesser General Public License for more details. |
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* |
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* You should have received a copy of the GNU Lesser General Public |
||||
* License along with FFmpeg; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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*/ |
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#include <stdint.h> |
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#include "dsputil_vis.h" |
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#include "libavutil/mem.h" |
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static const DECLARE_ALIGNED(8, int16_t, coeffs)[28] = { |
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- 1259,- 1259,- 1259,- 1259, |
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- 4989,- 4989,- 4989,- 4989, |
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-11045,-11045,-11045,-11045, |
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-19195,-19195,-19195,-19195, |
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-29126,-29126,-29126,-29126, |
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25080, 25080, 25080, 25080, |
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12785, 12785, 12785, 12785 |
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}; |
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static const DECLARE_ALIGNED(8, uint16_t, scale)[4] = { |
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65536>>6, 65536>>6, 65536>>6, 65536>>6 |
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}; |
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static const DECLARE_ALIGNED(8, uint16_t, rounder)[4] = { |
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1<<5, 1<<5, 1<<5, 1<<5 |
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}; |
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static const DECLARE_ALIGNED(8, uint16_t, expand)[4] = { |
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1<<14, 1<<14, 1<<14, 1<<14 |
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}; |
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|
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#define INIT_IDCT \ |
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"ldd [%1], %%f32 \n\t"\
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"ldd [%1+8], %%f34 \n\t"\
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"ldd [%1+16], %%f36 \n\t"\
|
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"ldd [%1+24], %%f38 \n\t"\
|
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"ldd [%1+32], %%f40 \n\t"\
|
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"ldd [%1+40], %%f42 \n\t"\
|
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"ldd [%1+48], %%f44 \n\t"\
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"ldd [%0], %%f46 \n\t"\
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"fzero %%f62 \n\t"\
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|
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#define LOADSCALE(in) \ |
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"ldd [" in "], %%f0 \n\t"\
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"ldd [" in "+16], %%f2 \n\t"\
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"ldd [" in "+32], %%f4 \n\t"\
|
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"ldd [" in "+48], %%f6 \n\t"\
|
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"ldd [" in "+64], %%f8 \n\t"\
|
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"ldd [" in "+80], %%f10 \n\t"\
|
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"ldd [" in "+96], %%f12 \n\t"\
|
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"ldd [" in "+112], %%f14 \n\t"\
|
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"fpadd16 %%f0, %%f0, %%f0 \n\t"\
|
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"fpadd16 %%f2, %%f2, %%f2 \n\t"\
|
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"fpadd16 %%f4, %%f4, %%f4 \n\t"\
|
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"fpadd16 %%f6, %%f6, %%f6 \n\t"\
|
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"fpadd16 %%f8, %%f8, %%f8 \n\t"\
|
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"fpadd16 %%f10, %%f10, %%f10 \n\t"\
|
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"fpadd16 %%f12, %%f12, %%f12 \n\t"\
|
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"fpadd16 %%f14, %%f14, %%f14 \n\t"\
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\
|
||||
"fpadd16 %%f0, %%f0, %%f0 \n\t"\
|
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"fpadd16 %%f2, %%f2, %%f2 \n\t"\
|
||||
"fpadd16 %%f4, %%f4, %%f4 \n\t"\
|
||||
"fpadd16 %%f6, %%f6, %%f6 \n\t"\
|
||||
"fpadd16 %%f8, %%f8, %%f8 \n\t"\
|
||||
"fpadd16 %%f10, %%f10, %%f10 \n\t"\
|
||||
"fpadd16 %%f12, %%f12, %%f12 \n\t"\
|
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"fpadd16 %%f14, %%f14, %%f14 \n\t"\
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\
|
||||
"fpadd16 %%f0, %%f0, %%f0 \n\t"\
|
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"fpadd16 %%f2, %%f2, %%f2 \n\t"\
|
||||
"fpadd16 %%f4, %%f4, %%f4 \n\t"\
|
||||
"fpadd16 %%f6, %%f6, %%f6 \n\t"\
|
||||
"fpadd16 %%f8, %%f8, %%f8 \n\t"\
|
||||
"fpadd16 %%f10, %%f10, %%f10 \n\t"\
|
||||
"fpadd16 %%f12, %%f12, %%f12 \n\t"\
|
||||
"fpadd16 %%f14, %%f14, %%f14 \n\t"\
|
||||
\
|
||||
"fpadd16 %%f0, %%f0, %%f0 \n\t"\
|
||||
"fpadd16 %%f2, %%f2, %%f2 \n\t"\
|
||||
"fpadd16 %%f4, %%f4, %%f4 \n\t"\
|
||||
"fpadd16 %%f6, %%f6, %%f6 \n\t"\
|
||||
"fpadd16 %%f8, %%f8, %%f8 \n\t"\
|
||||
"fpadd16 %%f10, %%f10, %%f10 \n\t"\
|
||||
"fpadd16 %%f12, %%f12, %%f12 \n\t"\
|
||||
"fpadd16 %%f14, %%f14, %%f14 \n\t"\
|
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|
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#define LOAD(in) \ |
||||
"ldd [" in "], %%f16 \n\t"\
|
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"ldd [" in "+8], %%f18 \n\t"\
|
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"ldd [" in "+16], %%f20 \n\t"\
|
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"ldd [" in "+24], %%f22 \n\t"\
|
||||
"ldd [" in "+32], %%f24 \n\t"\
|
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"ldd [" in "+40], %%f26 \n\t"\
|
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"ldd [" in "+48], %%f28 \n\t"\
|
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"ldd [" in "+56], %%f30 \n\t"\
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|
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#define TRANSPOSE \ |
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"fpmerge %%f16, %%f24, %%f0 \n\t"\
|
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"fpmerge %%f20, %%f28, %%f2 \n\t"\
|
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"fpmerge %%f17, %%f25, %%f4 \n\t"\
|
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"fpmerge %%f21, %%f29, %%f6 \n\t"\
|
||||
"fpmerge %%f18, %%f26, %%f8 \n\t"\
|
||||
"fpmerge %%f22, %%f30, %%f10 \n\t"\
|
||||
"fpmerge %%f19, %%f27, %%f12 \n\t"\
|
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"fpmerge %%f23, %%f31, %%f14 \n\t"\
|
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\
|
||||
"fpmerge %%f0, %%f2, %%f16 \n\t"\
|
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"fpmerge %%f1, %%f3, %%f18 \n\t"\
|
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"fpmerge %%f4, %%f6, %%f20 \n\t"\
|
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"fpmerge %%f5, %%f7, %%f22 \n\t"\
|
||||
"fpmerge %%f8, %%f10, %%f24 \n\t"\
|
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"fpmerge %%f9, %%f11, %%f26 \n\t"\
|
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"fpmerge %%f12, %%f14, %%f28 \n\t"\
|
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"fpmerge %%f13, %%f15, %%f30 \n\t"\
|
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\
|
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"fpmerge %%f16, %%f17, %%f0 \n\t"\
|
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"fpmerge %%f18, %%f19, %%f2 \n\t"\
|
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"fpmerge %%f20, %%f21, %%f4 \n\t"\
|
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"fpmerge %%f22, %%f23, %%f6 \n\t"\
|
||||
"fpmerge %%f24, %%f25, %%f8 \n\t"\
|
||||
"fpmerge %%f26, %%f27, %%f10 \n\t"\
|
||||
"fpmerge %%f28, %%f29, %%f12 \n\t"\
|
||||
"fpmerge %%f30, %%f31, %%f14 \n\t"\
|
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|
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#define IDCT4ROWS \ |
||||
/* 1. column */\
|
||||
"fmul8ulx16 %%f0, %%f38, %%f28 \n\t"\
|
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"for %%f4, %%f6, %%f60 \n\t"\
|
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"fmul8ulx16 %%f2, %%f32, %%f18 \n\t"\
|
||||
"fmul8ulx16 %%f2, %%f36, %%f22 \n\t"\
|
||||
"fmul8ulx16 %%f2, %%f40, %%f26 \n\t"\
|
||||
"fmul8ulx16 %%f2, %%f44, %%f30 \n\t"\
|
||||
\
|
||||
ADDROUNDER\
|
||||
\
|
||||
"fmul8sux16 %%f0, %%f38, %%f48 \n\t"\
|
||||
"fcmpd %%fcc0, %%f62, %%f60 \n\t"\
|
||||
"for %%f8, %%f10, %%f60 \n\t"\
|
||||
"fmul8sux16 %%f2, %%f32, %%f50 \n\t"\
|
||||
"fmul8sux16 %%f2, %%f36, %%f52 \n\t"\
|
||||
"fmul8sux16 %%f2, %%f40, %%f54 \n\t"\
|
||||
"fmul8sux16 %%f2, %%f44, %%f56 \n\t"\
|
||||
\
|
||||
"fpadd16 %%f48, %%f28, %%f28 \n\t"\
|
||||
"fcmpd %%fcc1, %%f62, %%f60 \n\t"\
|
||||
"for %%f12, %%f14, %%f60 \n\t"\
|
||||
"fpadd16 %%f50, %%f18, %%f18 \n\t"\
|
||||
"fpadd16 %%f52, %%f22, %%f22 \n\t"\
|
||||
"fpadd16 %%f54, %%f26, %%f26 \n\t"\
|
||||
"fpadd16 %%f56, %%f30, %%f30 \n\t"\
|
||||
\
|
||||
"fpadd16 %%f28, %%f0, %%f16 \n\t"\
|
||||
"fcmpd %%fcc2, %%f62, %%f60 \n\t"\
|
||||
"fpadd16 %%f28, %%f0, %%f20 \n\t"\
|
||||
"fpadd16 %%f28, %%f0, %%f24 \n\t"\
|
||||
"fpadd16 %%f28, %%f0, %%f28 \n\t"\
|
||||
"fpadd16 %%f18, %%f2, %%f18 \n\t"\
|
||||
"fpadd16 %%f22, %%f2, %%f22 \n\t"\
|
||||
/* 2. column */\
|
||||
"fbe %%fcc0, 3f \n\t"\
|
||||
"fpadd16 %%f26, %%f2, %%f26 \n\t"\
|
||||
"fmul8ulx16 %%f4, %%f34, %%f48 \n\t"\
|
||||
"fmul8ulx16 %%f4, %%f42, %%f50 \n\t"\
|
||||
"fmul8ulx16 %%f6, %%f36, %%f52 \n\t"\
|
||||
"fmul8ulx16 %%f6, %%f44, %%f54 \n\t"\
|
||||
"fmul8ulx16 %%f6, %%f32, %%f56 \n\t"\
|
||||
"fmul8ulx16 %%f6, %%f40, %%f58 \n\t"\
|
||||
\
|
||||
"fpadd16 %%f16, %%f48, %%f16 \n\t"\
|
||||
"fpadd16 %%f20, %%f50, %%f20 \n\t"\
|
||||
"fpsub16 %%f24, %%f50, %%f24 \n\t"\
|
||||
"fpsub16 %%f28, %%f48, %%f28 \n\t"\
|
||||
"fpadd16 %%f18, %%f52, %%f18 \n\t"\
|
||||
"fpsub16 %%f22, %%f54, %%f22 \n\t"\
|
||||
"fpsub16 %%f26, %%f56, %%f26 \n\t"\
|
||||
"fpsub16 %%f30, %%f58, %%f30 \n\t"\
|
||||
\
|
||||
"fmul8sux16 %%f4, %%f34, %%f48 \n\t"\
|
||||
"fmul8sux16 %%f4, %%f42, %%f50 \n\t"\
|
||||
"fmul8sux16 %%f6, %%f36, %%f52 \n\t"\
|
||||
"fmul8sux16 %%f6, %%f44, %%f54 \n\t"\
|
||||
"fmul8sux16 %%f6, %%f32, %%f56 \n\t"\
|
||||
"fmul8sux16 %%f6, %%f40, %%f58 \n\t"\
|
||||
\
|
||||
"fpadd16 %%f16, %%f48, %%f16 \n\t"\
|
||||
"fpadd16 %%f20, %%f50, %%f20 \n\t"\
|
||||
"fpsub16 %%f24, %%f50, %%f24 \n\t"\
|
||||
"fpsub16 %%f28, %%f48, %%f28 \n\t"\
|
||||
"fpadd16 %%f18, %%f52, %%f18 \n\t"\
|
||||
"fpsub16 %%f22, %%f54, %%f22 \n\t"\
|
||||
"fpsub16 %%f26, %%f56, %%f26 \n\t"\
|
||||
"fpsub16 %%f30, %%f58, %%f30 \n\t"\
|
||||
\
|
||||
"fpadd16 %%f16, %%f4, %%f16 \n\t"\
|
||||
"fpsub16 %%f28, %%f4, %%f28 \n\t"\
|
||||
"fpadd16 %%f18, %%f6, %%f18 \n\t"\
|
||||
"fpsub16 %%f26, %%f6, %%f26 \n\t"\
|
||||
/* 3. column */\
|
||||
"3: \n\t"\
|
||||
"fbe %%fcc1, 4f \n\t"\
|
||||
"fpsub16 %%f30, %%f6, %%f30 \n\t"\
|
||||
"fmul8ulx16 %%f8, %%f38, %%f48 \n\t"\
|
||||
"fmul8ulx16 %%f10, %%f40, %%f50 \n\t"\
|
||||
"fmul8ulx16 %%f10, %%f32, %%f52 \n\t"\
|
||||
"fmul8ulx16 %%f10, %%f44, %%f54 \n\t"\
|
||||
"fmul8ulx16 %%f10, %%f36, %%f56 \n\t"\
|
||||
\
|
||||
"fpadd16 %%f16, %%f48, %%f16 \n\t"\
|
||||
"fpsub16 %%f20, %%f48, %%f20 \n\t"\
|
||||
"fpsub16 %%f24, %%f48, %%f24 \n\t"\
|
||||
"fpadd16 %%f28, %%f48, %%f28 \n\t"\
|
||||
"fpadd16 %%f18, %%f50, %%f18 \n\t"\
|
||||
"fpsub16 %%f22, %%f52, %%f22 \n\t"\
|
||||
"fpadd16 %%f26, %%f54, %%f26 \n\t"\
|
||||
"fpadd16 %%f30, %%f56, %%f30 \n\t"\
|
||||
\
|
||||
"fmul8sux16 %%f8, %%f38, %%f48 \n\t"\
|
||||
"fmul8sux16 %%f10, %%f40, %%f50 \n\t"\
|
||||
"fmul8sux16 %%f10, %%f32, %%f52 \n\t"\
|
||||
"fmul8sux16 %%f10, %%f44, %%f54 \n\t"\
|
||||
"fmul8sux16 %%f10, %%f36, %%f56 \n\t"\
|
||||
\
|
||||
"fpadd16 %%f16, %%f48, %%f16 \n\t"\
|
||||
"fpsub16 %%f20, %%f48, %%f20 \n\t"\
|
||||
"fpsub16 %%f24, %%f48, %%f24 \n\t"\
|
||||
"fpadd16 %%f28, %%f48, %%f28 \n\t"\
|
||||
"fpadd16 %%f18, %%f50, %%f18 \n\t"\
|
||||
"fpsub16 %%f22, %%f52, %%f22 \n\t"\
|
||||
"fpadd16 %%f26, %%f54, %%f26 \n\t"\
|
||||
"fpadd16 %%f30, %%f56, %%f30 \n\t"\
|
||||
\
|
||||
"fpadd16 %%f16, %%f8, %%f16 \n\t"\
|
||||
"fpsub16 %%f20, %%f8, %%f20 \n\t"\
|
||||
"fpsub16 %%f24, %%f8, %%f24 \n\t"\
|
||||
"fpadd16 %%f28, %%f8, %%f28 \n\t"\
|
||||
"fpadd16 %%f18, %%f10, %%f18 \n\t"\
|
||||
"fpsub16 %%f22, %%f10, %%f22 \n\t"\
|
||||
/* 4. column */\
|
||||
"4: \n\t"\
|
||||
"fbe %%fcc2, 5f \n\t"\
|
||||
"fpadd16 %%f30, %%f10, %%f30 \n\t"\
|
||||
"fmul8ulx16 %%f12, %%f42, %%f48 \n\t"\
|
||||
"fmul8ulx16 %%f12, %%f34, %%f50 \n\t"\
|
||||
"fmul8ulx16 %%f14, %%f44, %%f52 \n\t"\
|
||||
"fmul8ulx16 %%f14, %%f40, %%f54 \n\t"\
|
||||
"fmul8ulx16 %%f14, %%f36, %%f56 \n\t"\
|
||||
"fmul8ulx16 %%f14, %%f32, %%f58 \n\t"\
|
||||
\
|
||||
"fpadd16 %%f16, %%f48, %%f16 \n\t"\
|
||||
"fpsub16 %%f20, %%f50, %%f20 \n\t"\
|
||||
"fpadd16 %%f24, %%f50, %%f24 \n\t"\
|
||||
"fpsub16 %%f28, %%f48, %%f28 \n\t"\
|
||||
"fpadd16 %%f18, %%f52, %%f18 \n\t"\
|
||||
"fpsub16 %%f22, %%f54, %%f22 \n\t"\
|
||||
"fpadd16 %%f26, %%f56, %%f26 \n\t"\
|
||||
"fpsub16 %%f30, %%f58, %%f30 \n\t"\
|
||||
\
|
||||
"fmul8sux16 %%f12, %%f42, %%f48 \n\t"\
|
||||
"fmul8sux16 %%f12, %%f34, %%f50 \n\t"\
|
||||
"fmul8sux16 %%f14, %%f44, %%f52 \n\t"\
|
||||
"fmul8sux16 %%f14, %%f40, %%f54 \n\t"\
|
||||
"fmul8sux16 %%f14, %%f36, %%f56 \n\t"\
|
||||
"fmul8sux16 %%f14, %%f32, %%f58 \n\t"\
|
||||
\
|
||||
"fpadd16 %%f16, %%f48, %%f16 \n\t"\
|
||||
"fpsub16 %%f20, %%f50, %%f20 \n\t"\
|
||||
"fpadd16 %%f24, %%f50, %%f24 \n\t"\
|
||||
"fpsub16 %%f28, %%f48, %%f28 \n\t"\
|
||||
"fpadd16 %%f18, %%f52, %%f18 \n\t"\
|
||||
"fpsub16 %%f22, %%f54, %%f22 \n\t"\
|
||||
"fpadd16 %%f26, %%f56, %%f26 \n\t"\
|
||||
"fpsub16 %%f30, %%f58, %%f30 \n\t"\
|
||||
\
|
||||
"fpsub16 %%f20, %%f12, %%f20 \n\t"\
|
||||
"fpadd16 %%f24, %%f12, %%f24 \n\t"\
|
||||
"fpsub16 %%f22, %%f14, %%f22 \n\t"\
|
||||
"fpadd16 %%f26, %%f14, %%f26 \n\t"\
|
||||
"fpsub16 %%f30, %%f14, %%f30 \n\t"\
|
||||
/* final butterfly */\
|
||||
"5: \n\t"\
|
||||
"fpsub16 %%f16, %%f18, %%f48 \n\t"\
|
||||
"fpsub16 %%f20, %%f22, %%f50 \n\t"\
|
||||
"fpsub16 %%f24, %%f26, %%f52 \n\t"\
|
||||
"fpsub16 %%f28, %%f30, %%f54 \n\t"\
|
||||
"fpadd16 %%f16, %%f18, %%f16 \n\t"\
|
||||
"fpadd16 %%f20, %%f22, %%f20 \n\t"\
|
||||
"fpadd16 %%f24, %%f26, %%f24 \n\t"\
|
||||
"fpadd16 %%f28, %%f30, %%f28 \n\t"\
|
||||
|
||||
#define STOREROWS(out) \ |
||||
"std %%f48, [" out "+112] \n\t"\
|
||||
"std %%f50, [" out "+96] \n\t"\
|
||||
"std %%f52, [" out "+80] \n\t"\
|
||||
"std %%f54, [" out "+64] \n\t"\
|
||||
"std %%f16, [" out "] \n\t"\
|
||||
"std %%f20, [" out "+16] \n\t"\
|
||||
"std %%f24, [" out "+32] \n\t"\
|
||||
"std %%f28, [" out "+48] \n\t"\
|
||||
|
||||
#define SCALEROWS \ |
||||
"fmul8sux16 %%f46, %%f48, %%f48 \n\t"\
|
||||
"fmul8sux16 %%f46, %%f50, %%f50 \n\t"\
|
||||
"fmul8sux16 %%f46, %%f52, %%f52 \n\t"\
|
||||
"fmul8sux16 %%f46, %%f54, %%f54 \n\t"\
|
||||
"fmul8sux16 %%f46, %%f16, %%f16 \n\t"\
|
||||
"fmul8sux16 %%f46, %%f20, %%f20 \n\t"\
|
||||
"fmul8sux16 %%f46, %%f24, %%f24 \n\t"\
|
||||
"fmul8sux16 %%f46, %%f28, %%f28 \n\t"\
|
||||
|
||||
#define PUTPIXELSCLAMPED(dest) \ |
||||
"fpack16 %%f48, %%f14 \n\t"\
|
||||
"fpack16 %%f50, %%f12 \n\t"\
|
||||
"fpack16 %%f16, %%f0 \n\t"\
|
||||
"fpack16 %%f20, %%f2 \n\t"\
|
||||
"fpack16 %%f24, %%f4 \n\t"\
|
||||
"fpack16 %%f28, %%f6 \n\t"\
|
||||
"fpack16 %%f54, %%f8 \n\t"\
|
||||
"fpack16 %%f52, %%f10 \n\t"\
|
||||
"st %%f0, [%3+" dest "] \n\t"\
|
||||
"st %%f2, [%5+" dest "] \n\t"\
|
||||
"st %%f4, [%6+" dest "] \n\t"\
|
||||
"st %%f6, [%7+" dest "] \n\t"\
|
||||
"st %%f8, [%8+" dest "] \n\t"\
|
||||
"st %%f10, [%9+" dest "] \n\t"\
|
||||
"st %%f12, [%10+" dest "] \n\t"\
|
||||
"st %%f14, [%11+" dest "] \n\t"\
|
||||
|
||||
#define ADDPIXELSCLAMPED(dest) \ |
||||
"ldd [%5], %%f18 \n\t"\
|
||||
"ld [%3+" dest"], %%f0 \n\t"\
|
||||
"ld [%6+" dest"], %%f2 \n\t"\
|
||||
"ld [%7+" dest"], %%f4 \n\t"\
|
||||
"ld [%8+" dest"], %%f6 \n\t"\
|
||||
"ld [%9+" dest"], %%f8 \n\t"\
|
||||
"ld [%10+" dest"], %%f10 \n\t"\
|
||||
"ld [%11+" dest"], %%f12 \n\t"\
|
||||
"ld [%12+" dest"], %%f14 \n\t"\
|
||||
"fmul8x16 %%f0, %%f18, %%f0 \n\t"\
|
||||
"fmul8x16 %%f2, %%f18, %%f2 \n\t"\
|
||||
"fmul8x16 %%f4, %%f18, %%f4 \n\t"\
|
||||
"fmul8x16 %%f6, %%f18, %%f6 \n\t"\
|
||||
"fmul8x16 %%f8, %%f18, %%f8 \n\t"\
|
||||
"fmul8x16 %%f10, %%f18, %%f10 \n\t"\
|
||||
"fmul8x16 %%f12, %%f18, %%f12 \n\t"\
|
||||
"fmul8x16 %%f14, %%f18, %%f14 \n\t"\
|
||||
"fpadd16 %%f0, %%f16, %%f0 \n\t"\
|
||||
"fpadd16 %%f2, %%f20, %%f2 \n\t"\
|
||||
"fpadd16 %%f4, %%f24, %%f4 \n\t"\
|
||||
"fpadd16 %%f6, %%f28, %%f6 \n\t"\
|
||||
"fpadd16 %%f8, %%f54, %%f8 \n\t"\
|
||||
"fpadd16 %%f10, %%f52, %%f10 \n\t"\
|
||||
"fpadd16 %%f12, %%f50, %%f12 \n\t"\
|
||||
"fpadd16 %%f14, %%f48, %%f14 \n\t"\
|
||||
"fpack16 %%f0, %%f0 \n\t"\
|
||||
"fpack16 %%f2, %%f2 \n\t"\
|
||||
"fpack16 %%f4, %%f4 \n\t"\
|
||||
"fpack16 %%f6, %%f6 \n\t"\
|
||||
"fpack16 %%f8, %%f8 \n\t"\
|
||||
"fpack16 %%f10, %%f10 \n\t"\
|
||||
"fpack16 %%f12, %%f12 \n\t"\
|
||||
"fpack16 %%f14, %%f14 \n\t"\
|
||||
"st %%f0, [%3+" dest "] \n\t"\
|
||||
"st %%f2, [%6+" dest "] \n\t"\
|
||||
"st %%f4, [%7+" dest "] \n\t"\
|
||||
"st %%f6, [%8+" dest "] \n\t"\
|
||||
"st %%f8, [%9+" dest "] \n\t"\
|
||||
"st %%f10, [%10+" dest "] \n\t"\
|
||||
"st %%f12, [%11+" dest "] \n\t"\
|
||||
"st %%f14, [%12+" dest "] \n\t"\
|
||||
|
||||
|
||||
void ff_simple_idct_vis(int16_t *data) { |
||||
int out1, out2, out3, out4; |
||||
DECLARE_ALIGNED(8, int16_t, temp)[8*8]; |
||||
|
||||
__asm__ volatile( |
||||
INIT_IDCT |
||||
|
||||
#define ADDROUNDER |
||||
|
||||
// shift right 16-4=12
|
||||
LOADSCALE("%2+8") |
||||
IDCT4ROWS |
||||
STOREROWS("%3+8") |
||||
LOADSCALE("%2+0") |
||||
IDCT4ROWS |
||||
"std %%f48, [%3+112] \n\t" |
||||
"std %%f50, [%3+96] \n\t" |
||||
"std %%f52, [%3+80] \n\t" |
||||
"std %%f54, [%3+64] \n\t" |
||||
|
||||
// shift right 16+4
|
||||
"ldd [%3+8], %%f18 \n\t" |
||||
"ldd [%3+24], %%f22 \n\t" |
||||
"ldd [%3+40], %%f26 \n\t" |
||||
"ldd [%3+56], %%f30 \n\t" |
||||
TRANSPOSE |
||||
IDCT4ROWS |
||||
SCALEROWS |
||||
STOREROWS("%2+0") |
||||
LOAD("%3+64") |
||||
TRANSPOSE |
||||
IDCT4ROWS |
||||
SCALEROWS |
||||
STOREROWS("%2+8") |
||||
|
||||
: "=r" (out1), "=r" (out2), "=r" (out3), "=r" (out4) |
||||
: "0" (scale), "1" (coeffs), "2" (data), "3" (temp) |
||||
); |
||||
} |
||||
|
||||
void ff_simple_idct_put_vis(uint8_t *dest, int line_size, int16_t *data) { |
||||
int out1, out2, out3, out4, out5; |
||||
int r1, r2, r3, r4, r5, r6, r7; |
||||
|
||||
__asm__ volatile( |
||||
"wr %%g0, 0x8, %%gsr \n\t" |
||||
|
||||
INIT_IDCT |
||||
|
||||
"add %3, %4, %5 \n\t" |
||||
"add %5, %4, %6 \n\t" |
||||
"add %6, %4, %7 \n\t" |
||||
"add %7, %4, %8 \n\t" |
||||
"add %8, %4, %9 \n\t" |
||||
"add %9, %4, %10 \n\t" |
||||
"add %10, %4, %11 \n\t" |
||||
|
||||
// shift right 16-4=12
|
||||
LOADSCALE("%2+8") |
||||
IDCT4ROWS |
||||
STOREROWS("%2+8") |
||||
LOADSCALE("%2+0") |
||||
IDCT4ROWS |
||||
"std %%f48, [%2+112] \n\t" |
||||
"std %%f50, [%2+96] \n\t" |
||||
"std %%f52, [%2+80] \n\t" |
||||
"std %%f54, [%2+64] \n\t" |
||||
|
||||
#undef ADDROUNDER |
||||
#define ADDROUNDER "fpadd16 %%f28, %%f46, %%f28 \n\t" |
||||
|
||||
// shift right 16+4
|
||||
"ldd [%2+8], %%f18 \n\t" |
||||
"ldd [%2+24], %%f22 \n\t" |
||||
"ldd [%2+40], %%f26 \n\t" |
||||
"ldd [%2+56], %%f30 \n\t" |
||||
TRANSPOSE |
||||
IDCT4ROWS |
||||
PUTPIXELSCLAMPED("0") |
||||
LOAD("%2+64") |
||||
TRANSPOSE |
||||
IDCT4ROWS |
||||
PUTPIXELSCLAMPED("4") |
||||
|
||||
: "=r" (out1), "=r" (out2), "=r" (out3), "=r" (out4), "=r" (out5), |
||||
"=r" (r1), "=r" (r2), "=r" (r3), "=r" (r4), "=r" (r5), "=r" (r6), "=r" (r7) |
||||
: "0" (rounder), "1" (coeffs), "2" (data), "3" (dest), "4" (line_size) |
||||
); |
||||
} |
||||
|
||||
void ff_simple_idct_add_vis(uint8_t *dest, int line_size, int16_t *data) { |
||||
int out1, out2, out3, out4, out5, out6; |
||||
int r1, r2, r3, r4, r5, r6, r7; |
||||
|
||||
__asm__ volatile( |
||||
"wr %%g0, 0x8, %%gsr \n\t" |
||||
|
||||
INIT_IDCT |
||||
|
||||
"add %3, %4, %6 \n\t" |
||||
"add %6, %4, %7 \n\t" |
||||
"add %7, %4, %8 \n\t" |
||||
"add %8, %4, %9 \n\t" |
||||
"add %9, %4, %10 \n\t" |
||||
"add %10, %4, %11 \n\t" |
||||
"add %11, %4, %12 \n\t" |
||||
|
||||
#undef ADDROUNDER |
||||
#define ADDROUNDER |
||||
|
||||
// shift right 16-4=12
|
||||
LOADSCALE("%2+8") |
||||
IDCT4ROWS |
||||
STOREROWS("%2+8") |
||||
LOADSCALE("%2+0") |
||||
IDCT4ROWS |
||||
"std %%f48, [%2+112] \n\t" |
||||
"std %%f50, [%2+96] \n\t" |
||||
"std %%f52, [%2+80] \n\t" |
||||
"std %%f54, [%2+64] \n\t" |
||||
|
||||
#undef ADDROUNDER |
||||
#define ADDROUNDER "fpadd16 %%f28, %%f46, %%f28 \n\t" |
||||
|
||||
// shift right 16+4
|
||||
"ldd [%2+8], %%f18 \n\t" |
||||
"ldd [%2+24], %%f22 \n\t" |
||||
"ldd [%2+40], %%f26 \n\t" |
||||
"ldd [%2+56], %%f30 \n\t" |
||||
TRANSPOSE |
||||
IDCT4ROWS |
||||
ADDPIXELSCLAMPED("0") |
||||
LOAD("%2+64") |
||||
TRANSPOSE |
||||
IDCT4ROWS |
||||
ADDPIXELSCLAMPED("4") |
||||
|
||||
: "=r" (out1), "=r" (out2), "=r" (out3), "=r" (out4), "=r" (out5), "=r" (out6), |
||||
"=r" (r1), "=r" (r2), "=r" (r3), "=r" (r4), "=r" (r5), "=r" (r6), "=r" (r7) |
||||
: "0" (rounder), "1" (coeffs), "2" (data), "3" (dest), "4" (line_size), "5" (expand) |
||||
); |
||||
} |
||||
@ -1,264 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2003 David S. Miller <davem@redhat.com> |
||||
* |
||||
* This file is part of FFmpeg. |
||||
* |
||||
* FFmpeg is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU Lesser General Public |
||||
* License as published by the Free Software Foundation; either |
||||
* version 2.1 of the License, or (at your option) any later version. |
||||
* |
||||
* FFmpeg is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
||||
* Lesser General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU Lesser General Public |
||||
* License along with FFmpeg; if not, write to the Free Software |
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
||||
*/ |
||||
|
||||
/* You may be asking why I hard-code the instruction opcodes and don't
|
||||
* use the normal VIS assembler mnenomics for the VIS instructions. |
||||
* |
||||
* The reason is that Sun, in their infinite wisdom, decided that a binary |
||||
* using a VIS instruction will cause it to be marked (in the ELF headers) |
||||
* as doing so, and this prevents the OS from loading such binaries if the |
||||
* current cpu doesn't have VIS. There is no way to easily override this |
||||
* behavior of the assembler that I am aware of. |
||||
* |
||||
* This totally defeats what libmpeg2 is trying to do which is allow a |
||||
* single binary to be created, and then detect the availability of VIS |
||||
* at runtime. |
||||
* |
||||
* I'm not saying that tainting the binary by default is bad, rather I'm |
||||
* saying that not providing a way to override this easily unnecessarily |
||||
* ties people's hands. |
||||
* |
||||
* Thus, we do the opcode encoding by hand and output 32-bit words in |
||||
* the assembler to keep the binary from becoming tainted. |
||||
*/ |
||||
|
||||
#ifndef AVCODEC_SPARC_VIS_H |
||||
#define AVCODEC_SPARC_VIS_H |
||||
|
||||
#define ACCEL_SPARC_VIS 1 |
||||
#define ACCEL_SPARC_VIS2 2 |
||||
|
||||
static inline int vis_level(void) |
||||
{ |
||||
int accel = 0; |
||||
accel |= ACCEL_SPARC_VIS; |
||||
accel |= ACCEL_SPARC_VIS2; |
||||
return accel; |
||||
} |
||||
|
||||
#define vis_opc_base ((0x1 << 31) | (0x36 << 19)) |
||||
#define vis_opf(X) ((X) << 5) |
||||
#define vis_sreg(X) (X) |
||||
#define vis_dreg(X) (((X)&0x1f)|((X)>>5)) |
||||
#define vis_rs1_s(X) (vis_sreg(X) << 14) |
||||
#define vis_rs1_d(X) (vis_dreg(X) << 14) |
||||
#define vis_rs2_s(X) (vis_sreg(X) << 0) |
||||
#define vis_rs2_d(X) (vis_dreg(X) << 0) |
||||
#define vis_rd_s(X) (vis_sreg(X) << 25) |
||||
#define vis_rd_d(X) (vis_dreg(X) << 25) |
||||
|
||||
#define vis_ss2s(opf,rs1,rs2,rd) \ |
||||
__asm__ volatile (".word %0" \
|
||||
: : "i" (vis_opc_base | vis_opf(opf) | \
|
||||
vis_rs1_s(rs1) | \
|
||||
vis_rs2_s(rs2) | \
|
||||
vis_rd_s(rd))) |
||||
|
||||
#define vis_dd2d(opf,rs1,rs2,rd) \ |
||||
__asm__ volatile (".word %0" \
|
||||
: : "i" (vis_opc_base | vis_opf(opf) | \
|
||||
vis_rs1_d(rs1) | \
|
||||
vis_rs2_d(rs2) | \
|
||||
vis_rd_d(rd))) |
||||
|
||||
#define vis_ss2d(opf,rs1,rs2,rd) \ |
||||
__asm__ volatile (".word %0" \
|
||||
: : "i" (vis_opc_base | vis_opf(opf) | \
|
||||
vis_rs1_s(rs1) | \
|
||||
vis_rs2_s(rs2) | \
|
||||
vis_rd_d(rd))) |
||||
|
||||
#define vis_sd2d(opf,rs1,rs2,rd) \ |
||||
__asm__ volatile (".word %0" \
|
||||
: : "i" (vis_opc_base | vis_opf(opf) | \
|
||||
vis_rs1_s(rs1) | \
|
||||
vis_rs2_d(rs2) | \
|
||||
vis_rd_d(rd))) |
||||
|
||||
#define vis_d2s(opf,rs2,rd) \ |
||||
__asm__ volatile (".word %0" \
|
||||
: : "i" (vis_opc_base | vis_opf(opf) | \
|
||||
vis_rs2_d(rs2) | \
|
||||
vis_rd_s(rd))) |
||||
|
||||
#define vis_s2d(opf,rs2,rd) \ |
||||
__asm__ volatile (".word %0" \
|
||||
: : "i" (vis_opc_base | vis_opf(opf) | \
|
||||
vis_rs2_s(rs2) | \
|
||||
vis_rd_d(rd))) |
||||
|
||||
#define vis_d12d(opf,rs1,rd) \ |
||||
__asm__ volatile (".word %0" \
|
||||
: : "i" (vis_opc_base | vis_opf(opf) | \
|
||||
vis_rs1_d(rs1) | \
|
||||
vis_rd_d(rd))) |
||||
|
||||
#define vis_d22d(opf,rs2,rd) \ |
||||
__asm__ volatile (".word %0" \
|
||||
: : "i" (vis_opc_base | vis_opf(opf) | \
|
||||
vis_rs2_d(rs2) | \
|
||||
vis_rd_d(rd))) |
||||
|
||||
#define vis_s12s(opf,rs1,rd) \ |
||||
__asm__ volatile (".word %0" \
|
||||
: : "i" (vis_opc_base | vis_opf(opf) | \
|
||||
vis_rs1_s(rs1) | \
|
||||
vis_rd_s(rd))) |
||||
|
||||
#define vis_s22s(opf,rs2,rd) \ |
||||
__asm__ volatile (".word %0" \
|
||||
: : "i" (vis_opc_base | vis_opf(opf) | \
|
||||
vis_rs2_s(rs2) | \
|
||||
vis_rd_s(rd))) |
||||
|
||||
#define vis_s(opf,rd) \ |
||||
__asm__ volatile (".word %0" \
|
||||
: : "i" (vis_opc_base | vis_opf(opf) | \
|
||||
vis_rd_s(rd))) |
||||
|
||||
#define vis_d(opf,rd) \ |
||||
__asm__ volatile (".word %0" \
|
||||
: : "i" (vis_opc_base | vis_opf(opf) | \
|
||||
vis_rd_d(rd))) |
||||
|
||||
#define vis_r2m(op,rd,mem) \ |
||||
__asm__ volatile (#op "\t%%f" #rd ", [%0]" : : "r" (&(mem)) ) |
||||
|
||||
#define vis_r2m_2(op,rd,mem1,mem2) \ |
||||
__asm__ volatile (#op "\t%%f" #rd ", [%0 + %1]" : : "r" (mem1), "r" (mem2) ) |
||||
|
||||
#define vis_m2r(op,mem,rd) \ |
||||
__asm__ volatile (#op "\t[%0], %%f" #rd : : "r" (&(mem)) ) |
||||
|
||||
#define vis_m2r_2(op,mem1,mem2,rd) \ |
||||
__asm__ volatile (#op "\t[%0 + %1], %%f" #rd : : "r" (mem1), "r" (mem2) ) |
||||
|
||||
static inline void vis_set_gsr(unsigned int val) |
||||
{ |
||||
__asm__ volatile("mov %0,%%asr19" |
||||
: : "r" (val)); |
||||
} |
||||
|
||||
#define VIS_GSR_ALIGNADDR_MASK 0x0000007 |
||||
#define VIS_GSR_ALIGNADDR_SHIFT 0 |
||||
#define VIS_GSR_SCALEFACT_MASK 0x0000078 |
||||
#define VIS_GSR_SCALEFACT_SHIFT 3 |
||||
|
||||
#define vis_ld32(mem,rs1) vis_m2r(ld, mem, rs1) |
||||
#define vis_ld32_2(mem1,mem2,rs1) vis_m2r_2(ld, mem1, mem2, rs1) |
||||
#define vis_st32(rs1,mem) vis_r2m(st, rs1, mem) |
||||
#define vis_st32_2(rs1,mem1,mem2) vis_r2m_2(st, rs1, mem1, mem2) |
||||
#define vis_ld64(mem,rs1) vis_m2r(ldd, mem, rs1) |
||||
#define vis_ld64_2(mem1,mem2,rs1) vis_m2r_2(ldd, mem1, mem2, rs1) |
||||
#define vis_st64(rs1,mem) vis_r2m(std, rs1, mem) |
||||
#define vis_st64_2(rs1,mem1,mem2) vis_r2m_2(std, rs1, mem1, mem2) |
||||
|
||||
/* 16 and 32 bit partitioned addition and subtraction. The normal
|
||||
* versions perform 4 16-bit or 2 32-bit additions or subtractions. |
||||
* The 's' versions perform 2 16-bit or 1 32-bit additions or |
||||
* subtractions. |
||||
*/ |
||||
|
||||
#define vis_padd16(rs1,rs2,rd) vis_dd2d(0x50, rs1, rs2, rd) |
||||
#define vis_padd16s(rs1,rs2,rd) vis_ss2s(0x51, rs1, rs2, rd) |
||||
#define vis_padd32(rs1,rs2,rd) vis_dd2d(0x52, rs1, rs2, rd) |
||||
#define vis_padd32s(rs1,rs2,rd) vis_ss2s(0x53, rs1, rs2, rd) |
||||
#define vis_psub16(rs1,rs2,rd) vis_dd2d(0x54, rs1, rs2, rd) |
||||
#define vis_psub16s(rs1,rs2,rd) vis_ss2s(0x55, rs1, rs2, rd) |
||||
#define vis_psub32(rs1,rs2,rd) vis_dd2d(0x56, rs1, rs2, rd) |
||||
#define vis_psub32s(rs1,rs2,rd) vis_ss2s(0x57, rs1, rs2, rd) |
||||
|
||||
/* Pixel formatting instructions. */ |
||||
|
||||
#define vis_pack16(rs2,rd) vis_d2s( 0x3b, rs2, rd) |
||||
#define vis_pack32(rs1,rs2,rd) vis_dd2d(0x3a, rs1, rs2, rd) |
||||
#define vis_packfix(rs2,rd) vis_d2s( 0x3d, rs2, rd) |
||||
#define vis_expand(rs2,rd) vis_s2d( 0x4d, rs2, rd) |
||||
#define vis_pmerge(rs1,rs2,rd) vis_ss2d(0x4b, rs1, rs2, rd) |
||||
|
||||
/* Partitioned multiply instructions. */ |
||||
|
||||
#define vis_mul8x16(rs1,rs2,rd) vis_sd2d(0x31, rs1, rs2, rd) |
||||
#define vis_mul8x16au(rs1,rs2,rd) vis_ss2d(0x33, rs1, rs2, rd) |
||||
#define vis_mul8x16al(rs1,rs2,rd) vis_ss2d(0x35, rs1, rs2, rd) |
||||
#define vis_mul8sux16(rs1,rs2,rd) vis_dd2d(0x36, rs1, rs2, rd) |
||||
#define vis_mul8ulx16(rs1,rs2,rd) vis_dd2d(0x37, rs1, rs2, rd) |
||||
#define vis_muld8sux16(rs1,rs2,rd) vis_ss2d(0x38, rs1, rs2, rd) |
||||
#define vis_muld8ulx16(rs1,rs2,rd) vis_ss2d(0x39, rs1, rs2, rd) |
||||
|
||||
/* Alignment instructions. */ |
||||
|
||||
static inline const void *vis_alignaddr(const void *ptr) |
||||
{ |
||||
__asm__ volatile("alignaddr %0, %%g0, %0" |
||||
: "=&r" (ptr) |
||||
: "0" (ptr)); |
||||
|
||||
return ptr; |
||||
} |
||||
|
||||
static inline void vis_alignaddr_g0(void *ptr) |
||||
{ |
||||
__asm__ volatile("alignaddr %0, %%g0, %%g0" |
||||
: : "r" (ptr)); |
||||
} |
||||
|
||||
#define vis_faligndata(rs1,rs2,rd) vis_dd2d(0x48, rs1, rs2, rd) |
||||
|
||||
/* Logical operate instructions. */ |
||||
|
||||
#define vis_fzero(rd) vis_d( 0x60, rd) |
||||
#define vis_fzeros(rd) vis_s( 0x61, rd) |
||||
#define vis_fone(rd) vis_d( 0x7e, rd) |
||||
#define vis_fones(rd) vis_s( 0x7f, rd) |
||||
#define vis_src1(rs1,rd) vis_d12d(0x74, rs1, rd) |
||||
#define vis_src1s(rs1,rd) vis_s12s(0x75, rs1, rd) |
||||
#define vis_src2(rs2,rd) vis_d22d(0x78, rs2, rd) |
||||
#define vis_src2s(rs2,rd) vis_s22s(0x79, rs2, rd) |
||||
#define vis_not1(rs1,rd) vis_d12d(0x6a, rs1, rd) |
||||
#define vis_not1s(rs1,rd) vis_s12s(0x6b, rs1, rd) |
||||
#define vis_not2(rs2,rd) vis_d22d(0x66, rs2, rd) |
||||
#define vis_not2s(rs2,rd) vis_s22s(0x67, rs2, rd) |
||||
#define vis_or(rs1,rs2,rd) vis_dd2d(0x7c, rs1, rs2, rd) |
||||
#define vis_ors(rs1,rs2,rd) vis_ss2s(0x7d, rs1, rs2, rd) |
||||
#define vis_nor(rs1,rs2,rd) vis_dd2d(0x62, rs1, rs2, rd) |
||||
#define vis_nors(rs1,rs2,rd) vis_ss2s(0x63, rs1, rs2, rd) |
||||
#define vis_and(rs1,rs2,rd) vis_dd2d(0x70, rs1, rs2, rd) |
||||
#define vis_ands(rs1,rs2,rd) vis_ss2s(0x71, rs1, rs2, rd) |
||||
#define vis_nand(rs1,rs2,rd) vis_dd2d(0x6e, rs1, rs2, rd) |
||||
#define vis_nands(rs1,rs2,rd) vis_ss2s(0x6f, rs1, rs2, rd) |
||||
#define vis_xor(rs1,rs2,rd) vis_dd2d(0x6c, rs1, rs2, rd) |
||||
#define vis_xors(rs1,rs2,rd) vis_ss2s(0x6d, rs1, rs2, rd) |
||||
#define vis_xnor(rs1,rs2,rd) vis_dd2d(0x72, rs1, rs2, rd) |
||||
#define vis_xnors(rs1,rs2,rd) vis_ss2s(0x73, rs1, rs2, rd) |
||||
#define vis_ornot1(rs1,rs2,rd) vis_dd2d(0x7a, rs1, rs2, rd) |
||||
#define vis_ornot1s(rs1,rs2,rd) vis_ss2s(0x7b, rs1, rs2, rd) |
||||
#define vis_ornot2(rs1,rs2,rd) vis_dd2d(0x76, rs1, rs2, rd) |
||||
#define vis_ornot2s(rs1,rs2,rd) vis_ss2s(0x77, rs1, rs2, rd) |
||||
#define vis_andnot1(rs1,rs2,rd) vis_dd2d(0x68, rs1, rs2, rd) |
||||
#define vis_andnot1s(rs1,rs2,rd) vis_ss2s(0x69, rs1, rs2, rd) |
||||
#define vis_andnot2(rs1,rs2,rd) vis_dd2d(0x64, rs1, rs2, rd) |
||||
#define vis_andnot2s(rs1,rs2,rd) vis_ss2s(0x65, rs1, rs2, rd) |
||||
|
||||
/* Pixel component distance. */ |
||||
|
||||
#define vis_pdist(rs1,rs2,rd) vis_dd2d(0x3e, rs1, rs2, rd) |
||||
|
||||
#endif /* AVCODEC_SPARC_VIS_H */ |
||||
@ -1 +0,0 @@ |
||||
VIS-OBJS += sparc/yuv2rgb_vis.o \
|
||||
@ -1,212 +0,0 @@ |
||||
/*
|
||||
* VIS optimized software YUV to RGB converter |
||||
* Copyright (c) 2007 Denes Balatoni <dbalatoni@programozo.hu> |
||||
* |
||||
* This file is part of FFmpeg. |
||||
* |
||||
* FFmpeg is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU Lesser General Public |
||||
* License as published by the Free Software Foundation; either |
||||
* version 2.1 of the License, or (at your option) any later version. |
||||
* |
||||
* FFmpeg is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
||||
* Lesser General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU Lesser General Public |
||||
* License along with FFmpeg; if not, write to the Free Software |
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
||||
*/ |
||||
|
||||
#include <inttypes.h> |
||||
#include <stdlib.h> |
||||
|
||||
#include "libavutil/attributes.h" |
||||
#include "libswscale/swscale.h" |
||||
#include "libswscale/swscale_internal.h" |
||||
|
||||
#define YUV2RGB_INIT \ |
||||
"wr %%g0, 0x10, %%gsr \n\t" \
|
||||
"ldd [%5], %%f32 \n\t" \
|
||||
"ldd [%5 + 8], %%f34 \n\t" \
|
||||
"ldd [%5 + 16], %%f36 \n\t" \
|
||||
"ldd [%5 + 24], %%f38 \n\t" \
|
||||
"ldd [%5 + 32], %%f40 \n\t" \
|
||||
"ldd [%5 + 40], %%f42 \n\t" \
|
||||
"ldd [%5 + 48], %%f44 \n\t" \
|
||||
"ldd [%5 + 56], %%f46 \n\t" \
|
||||
"ldd [%5 + 64], %%f48 \n\t" \
|
||||
"ldd [%5 + 72], %%f50 \n\t" |
||||
|
||||
#define YUV2RGB_KERNEL \ |
||||
/* ^^^^ f0=Y f3=u f5=v */ \
|
||||
"fmul8x16 %%f3, %%f48, %%f6 \n\t" \
|
||||
"fmul8x16 %%f19, %%f48, %%f22 \n\t" \
|
||||
"fmul8x16 %%f5, %%f44, %%f8 \n\t" \
|
||||
"fmul8x16 %%f21, %%f44, %%f24 \n\t" \
|
||||
"fmul8x16 %%f0, %%f42, %%f0 \n\t" \
|
||||
"fmul8x16 %%f16, %%f42, %%f16 \n\t" \
|
||||
"fmul8x16 %%f3, %%f50, %%f2 \n\t" \
|
||||
"fmul8x16 %%f19, %%f50, %%f18 \n\t" \
|
||||
"fmul8x16 %%f5, %%f46, %%f4 \n\t" \
|
||||
"fmul8x16 %%f21, %%f46, %%f20 \n\t" \
|
||||
\
|
||||
"fpsub16 %%f6, %%f34, %%f6 \n\t" /* 1 */ \
|
||||
"fpsub16 %%f22, %%f34, %%f22 \n\t" /* 1 */ \
|
||||
"fpsub16 %%f8, %%f38, %%f8 \n\t" /* 3 */ \
|
||||
"fpsub16 %%f24, %%f38, %%f24 \n\t" /* 3 */ \
|
||||
"fpsub16 %%f0, %%f32, %%f0 \n\t" /* 0 */ \
|
||||
"fpsub16 %%f16, %%f32, %%f16 \n\t" /* 0 */ \
|
||||
"fpsub16 %%f2, %%f36, %%f2 \n\t" /* 2 */ \
|
||||
"fpsub16 %%f18, %%f36, %%f18 \n\t" /* 2 */ \
|
||||
"fpsub16 %%f4, %%f40, %%f4 \n\t" /* 4 */ \
|
||||
"fpsub16 %%f20, %%f40, %%f20 \n\t" /* 4 */ \
|
||||
\
|
||||
"fpadd16 %%f0, %%f8, %%f8 \n\t" /* Gt */ \
|
||||
"fpadd16 %%f16, %%f24, %%f24 \n\t" /* Gt */ \
|
||||
"fpadd16 %%f0, %%f4, %%f4 \n\t" /* R */ \
|
||||
"fpadd16 %%f16, %%f20, %%f20 \n\t" /* R */ \
|
||||
"fpadd16 %%f0, %%f6, %%f6 \n\t" /* B */ \
|
||||
"fpadd16 %%f16, %%f22, %%f22 \n\t" /* B */ \
|
||||
"fpadd16 %%f8, %%f2, %%f2 \n\t" /* G */ \
|
||||
"fpadd16 %%f24, %%f18, %%f18 \n\t" /* G */ \
|
||||
\
|
||||
"fpack16 %%f4, %%f4 \n\t" \
|
||||
"fpack16 %%f20, %%f20 \n\t" \
|
||||
"fpack16 %%f6, %%f6 \n\t" \
|
||||
"fpack16 %%f22, %%f22 \n\t" \
|
||||
"fpack16 %%f2, %%f2 \n\t" \
|
||||
"fpack16 %%f18, %%f18 \n\t" |
||||
|
||||
// FIXME: must be changed to set alpha to 255 instead of 0
|
||||
static int vis_420P_ARGB32(SwsContext *c, uint8_t *src[], int srcStride[], |
||||
int srcSliceY, int srcSliceH, |
||||
uint8_t *dst[], int dstStride[]) |
||||
{ |
||||
int y, out1, out2, out3, out4, out5, out6; |
||||
|
||||
for (y = 0; y < srcSliceH; ++y) |
||||
__asm__ volatile ( |
||||
YUV2RGB_INIT |
||||
"wr %%g0, 0xd2, %%asi \n\t" /* ASI_FL16_P */ |
||||
"1: \n\t" |
||||
"ldda [%1] %%asi, %%f2 \n\t" |
||||
"ldda [%1 + 2] %%asi, %%f18 \n\t" |
||||
"ldda [%2] %%asi, %%f4 \n\t" |
||||
"ldda [%2 + 2] %%asi, %%f20 \n\t" |
||||
"ld [%0], %%f0 \n\t" |
||||
"ld [%0+4], %%f16 \n\t" |
||||
"fpmerge %%f3, %%f3, %%f2 \n\t" |
||||
"fpmerge %%f19, %%f19, %%f18 \n\t" |
||||
"fpmerge %%f5, %%f5, %%f4 \n\t" |
||||
"fpmerge %%f21, %%f21, %%f20 \n\t" |
||||
YUV2RGB_KERNEL |
||||
"fzero %%f0 \n\t" |
||||
"fpmerge %%f4, %%f6, %%f8 \n\t" // r, b, t1
|
||||
"fpmerge %%f20, %%f22, %%f24 \n\t" // r, b, t1
|
||||
"fpmerge %%f0, %%f2, %%f10 \n\t" // 0, g, t2
|
||||
"fpmerge %%f0, %%f18, %%f26 \n\t" // 0, g, t2
|
||||
"fpmerge %%f10, %%f8, %%f4 \n\t" // t2, t1, msb
|
||||
"fpmerge %%f26, %%f24, %%f20 \n\t" // t2, t1, msb
|
||||
"fpmerge %%f11, %%f9, %%f6 \n\t" // t2, t1, lsb
|
||||
"fpmerge %%f27, %%f25, %%f22 \n\t" // t2, t1, lsb
|
||||
"std %%f4, [%3] \n\t" |
||||
"std %%f20, [%3 + 16] \n\t" |
||||
"std %%f6, [%3 + 8] \n\t" |
||||
"std %%f22, [%3 + 24] \n\t" |
||||
|
||||
"add %0, 8, %0 \n\t" |
||||
"add %1, 4, %1 \n\t" |
||||
"add %2, 4, %2 \n\t" |
||||
"subcc %4, 8, %4 \n\t" |
||||
"bne 1b \n\t" |
||||
"add %3, 32, %3 \n\t" // delay slot
|
||||
: "=r" (out1), "=r" (out2), "=r" (out3), "=r" (out4), "=r" (out5), "=r" (out6) |
||||
: "0" (src[0] + (y + srcSliceY) * srcStride[0]), "1" (src[1] + ((y + srcSliceY) >> 1) * srcStride[1]), |
||||
"2" (src[2] + ((y + srcSliceY) >> 1) * srcStride[2]), "3" (dst[0] + (y + srcSliceY) * dstStride[0]), |
||||
"4" (c->dstW), |
||||
"5" (c->sparc_coeffs) |
||||
); |
||||
|
||||
return srcSliceH; |
||||
} |
||||
|
||||
// FIXME: must be changed to set alpha to 255 instead of 0
|
||||
static int vis_422P_ARGB32(SwsContext *c, uint8_t *src[], int srcStride[], |
||||
int srcSliceY, int srcSliceH, |
||||
uint8_t *dst[], int dstStride[]) |
||||
{ |
||||
int y, out1, out2, out3, out4, out5, out6; |
||||
|
||||
for (y = 0; y < srcSliceH; ++y) |
||||
__asm__ volatile ( |
||||
YUV2RGB_INIT |
||||
"wr %%g0, 0xd2, %%asi \n\t" /* ASI_FL16_P */ |
||||
"1: \n\t" |
||||
"ldda [%1] %%asi, %%f2 \n\t" |
||||
"ldda [%1 + 2] %%asi, %%f18 \n\t" |
||||
"ldda [%2] %%asi, %%f4 \n\t" |
||||
"ldda [%2 + 2] %%asi, %%f20 \n\t" |
||||
"ld [%0], %%f0 \n\t" |
||||
"ld [%0 + 4], %%f16 \n\t" |
||||
"fpmerge %%f3, %%f3, %%f2 \n\t" |
||||
"fpmerge %%f19, %%f19, %%f18 \n\t" |
||||
"fpmerge %%f5, %%f5, %%f4 \n\t" |
||||
"fpmerge %%f21, %%f21, %%f20 \n\t" |
||||
YUV2RGB_KERNEL |
||||
"fzero %%f0 \n\t" |
||||
"fpmerge %%f4, %%f6, %%f8 \n\t" // r,b,t1
|
||||
"fpmerge %%f20, %%f22, %%f24 \n\t" // r,b,t1
|
||||
"fpmerge %%f0, %%f2, %%f10 \n\t" // 0,g,t2
|
||||
"fpmerge %%f0, %%f18, %%f26 \n\t" // 0,g,t2
|
||||
"fpmerge %%f10, %%f8, %%f4 \n\t" // t2,t1,msb
|
||||
"fpmerge %%f26, %%f24, %%f20 \n\t" // t2,t1,msb
|
||||
"fpmerge %%f11, %%f9, %%f6 \n\t" // t2,t1,lsb
|
||||
"fpmerge %%f27, %%f25, %%f22 \n\t" // t2,t1,lsb
|
||||
"std %%f4, [%3] \n\t" |
||||
"std %%f20, [%3 + 16] \n\t" |
||||
"std %%f6, [%3 + 8] \n\t" |
||||
"std %%f22, [%3 + 24] \n\t" |
||||
|
||||
"add %0, 8, %0 \n\t" |
||||
"add %1, 4, %1 \n\t" |
||||
"add %2, 4, %2 \n\t" |
||||
"subcc %4, 8, %4 \n\t" |
||||
"bne 1b \n\t" |
||||
"add %3, 32, %3 \n\t" //delay slot
|
||||
: "=r" (out1), "=r" (out2), "=r" (out3), "=r" (out4), "=r" (out5), "=r" (out6) |
||||
: "0" (src[0] + (y + srcSliceY) * srcStride[0]), "1" (src[1] + (y + srcSliceY) * srcStride[1]), |
||||
"2" (src[2] + (y + srcSliceY) * srcStride[2]), "3" (dst[0] + (y + srcSliceY) * dstStride[0]), |
||||
"4" (c->dstW), |
||||
"5" (c->sparc_coeffs) |
||||
); |
||||
|
||||
return srcSliceH; |
||||
} |
||||
|
||||
av_cold SwsFunc ff_yuv2rgb_init_vis(SwsContext *c) |
||||
{ |
||||
c->sparc_coeffs[5] = c->yCoeff; |
||||
c->sparc_coeffs[6] = c->vgCoeff; |
||||
c->sparc_coeffs[7] = c->vrCoeff; |
||||
c->sparc_coeffs[8] = c->ubCoeff; |
||||
c->sparc_coeffs[9] = c->ugCoeff; |
||||
|
||||
c->sparc_coeffs[0] = (((int16_t)c->yOffset * (int16_t)c->yCoeff >> 11) & 0xffff) * 0x0001000100010001ULL; |
||||
c->sparc_coeffs[1] = (((int16_t)c->uOffset * (int16_t)c->ubCoeff >> 11) & 0xffff) * 0x0001000100010001ULL; |
||||
c->sparc_coeffs[2] = (((int16_t)c->uOffset * (int16_t)c->ugCoeff >> 11) & 0xffff) * 0x0001000100010001ULL; |
||||
c->sparc_coeffs[3] = (((int16_t)c->vOffset * (int16_t)c->vgCoeff >> 11) & 0xffff) * 0x0001000100010001ULL; |
||||
c->sparc_coeffs[4] = (((int16_t)c->vOffset * (int16_t)c->vrCoeff >> 11) & 0xffff) * 0x0001000100010001ULL; |
||||
|
||||
if (c->dstFormat == AV_PIX_FMT_RGB32 && c->srcFormat == AV_PIX_FMT_YUV422P && (c->dstW & 7) == 0) { |
||||
av_log(c, AV_LOG_INFO, |
||||
"SPARC VIS accelerated YUV422P -> RGB32 (WARNING: alpha value is wrong)\n"); |
||||
return vis_422P_ARGB32; |
||||
} else if (c->dstFormat == AV_PIX_FMT_RGB32 && c->srcFormat == AV_PIX_FMT_YUV420P && (c->dstW & 7) == 0) { |
||||
av_log(c, AV_LOG_INFO, |
||||
"SPARC VIS accelerated YUV420P -> RGB32 (WARNING: alpha value is wrong)\n"); |
||||
return vis_420P_ARGB32; |
||||
} |
||||
return NULL; |
||||
} |
||||
Loading…
Reference in new issue