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;******************************************************************************
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;* SIMD-optimized functions for the DCA decoder
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;* Copyright (C) 2016 James Almer
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "libavutil/x86/x86util.asm"
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SECTION .text
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%define sizeof_float 4
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%define FMA3_OFFSET (8 * cpuflag(fma3) * ARCH_X86_64)
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%macro LFE_FIR0_FLOAT 0
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cglobal lfe_fir0_float, 4, 6, 12 + cpuflag(fma3)*4, samples, lfe, coeff, nblocks, cnt1, cnt2
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shr nblocksd, 1
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sub lfeq, 7*sizeof_float
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mov cnt1d, 32*sizeof_float
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mov cnt2d, 32*sizeof_float-8-FMA3_OFFSET
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lea coeffq, [coeffq+cnt1q*8]
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add samplesq, cnt1q
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neg cnt1q
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.loop:
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%if cpuflag(avx)
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cvtdq2ps m4, [lfeq+16]
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cvtdq2ps m5, [lfeq ]
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shufps m7, m4, m4, q0123
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shufps m6, m5, m5, q0123
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%elif cpuflag(sse2)
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movu m4, [lfeq+16]
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movu m5, [lfeq ]
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cvtdq2ps m4, m4
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cvtdq2ps m5, m5
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pshufd m7, m4, q0123
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pshufd m6, m5, q0123
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%else
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cvtpi2ps m4, [lfeq+16]
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cvtpi2ps m0, [lfeq+24]
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cvtpi2ps m5, [lfeq ]
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cvtpi2ps m1, [lfeq+8 ]
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shufps m4, m0, q1010
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shufps m5, m1, q1010
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shufps m7, m4, m4, q0123
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shufps m6, m5, m5, q0123
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%endif
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.inner_loop:
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%if ARCH_X86_64
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movaps m8, [coeffq+cnt1q*8 ]
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movaps m9, [coeffq+cnt1q*8+16]
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movaps m10, [coeffq+cnt1q*8+32]
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movaps m11, [coeffq+cnt1q*8+48]
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%if cpuflag(fma3)
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movaps m12, [coeffq+cnt1q*8+64]
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movaps m13, [coeffq+cnt1q*8+80]
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movaps m14, [coeffq+cnt1q*8+96]
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movaps m15, [coeffq+cnt1q*8+112]
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mulps m0, m7, m8
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mulps m1, m7, m10
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mulps m2, m7, m12
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mulps m3, m7, m14
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fmaddps m0, m6, m9, m0
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fmaddps m1, m6, m11, m1
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fmaddps m2, m6, m13, m2
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fmaddps m3, m6, m15, m3
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haddps m0, m1
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haddps m2, m3
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haddps m0, m2
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movaps [samplesq+cnt1q], m0
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%else
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mulps m0, m7, m8
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mulps m1, m6, m9
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mulps m2, m7, m10
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mulps m3, m6, m11
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addps m0, m1
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addps m2, m3
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unpckhps m3, m0, m2
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unpcklps m0, m2
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addps m3, m0
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movhlps m2, m3
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addps m2, m3
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movlps [samplesq+cnt1q], m2
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%endif
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%else ; ARCH_X86_32
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%if cpuflag(fma3)
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mulps m0, m7, [coeffq+cnt1q*8 ]
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movaps m1, [coeffq+cnt1q*8+16]
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mulps m2, m7, [coeffq+cnt1q*8+32]
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fmaddps m0, m6, m1, m0
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fmaddps m2, m6, [coeffq+cnt1q*8+48], m2
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%else
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mulps m0, m7, [coeffq+cnt1q*8 ]
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mulps m1, m6, [coeffq+cnt1q*8+16]
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mulps m2, m7, [coeffq+cnt1q*8+32]
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mulps m3, m6, [coeffq+cnt1q*8+48]
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addps m0, m1
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addps m2, m3
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%endif
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unpckhps m3, m0, m2
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unpcklps m0, m2
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addps m3, m0
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movhlps m2, m3
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addps m2, m3
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movlps [samplesq+cnt1q], m2
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%endif; ARCH
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%if ARCH_X86_64
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%if cpuflag(fma3)
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mulps m8, m5
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mulps m10, m5
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mulps m12, m5
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mulps m14, m5
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fmaddps m8, m4, m9, m8
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fmaddps m10, m4, m11, m10
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fmaddps m12, m4, m13, m12
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fmaddps m14, m4, m15, m14
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haddps m10, m8
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haddps m14, m12
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haddps m14, m10
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movaps [samplesq+cnt2q], m14
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%else
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mulps m8, m5
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mulps m9, m4
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mulps m10, m5
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mulps m11, m4
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addps m8, m9
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addps m10, m11
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unpckhps m11, m10, m8
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unpcklps m10, m8
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addps m11, m10
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movhlps m8, m11
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addps m8, m11
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movlps [samplesq+cnt2q], m8
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%endif
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%else ; ARCH_X86_32
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%if cpuflag(fma3)
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mulps m0, m5, [coeffq+cnt1q*8 ]
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mulps m2, m5, [coeffq+cnt1q*8+32]
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fmaddps m0, m4, m1, m0
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fmaddps m2, m4, [coeffq+cnt1q*8+48], m2
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%else
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mulps m0, m5, [coeffq+cnt1q*8 ]
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mulps m1, m4, [coeffq+cnt1q*8+16]
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mulps m2, m5, [coeffq+cnt1q*8+32]
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mulps m3, m4, [coeffq+cnt1q*8+48]
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addps m0, m1
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addps m2, m3
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%endif
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unpckhps m3, m2, m0
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unpcklps m2, m0
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addps m3, m2
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movhlps m0, m3
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addps m0, m3
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movlps [samplesq+cnt2q], m0
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%endif; ARCH
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sub cnt2d, 8 + FMA3_OFFSET
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add cnt1q, 8 + FMA3_OFFSET
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jl .inner_loop
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add lfeq, 4
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add samplesq, 64*sizeof_float
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mov cnt1q, -32*sizeof_float
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mov cnt2d, 32*sizeof_float-8-FMA3_OFFSET
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sub nblocksd, 1
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jg .loop
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RET
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%endmacro
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%if ARCH_X86_32
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INIT_XMM sse
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LFE_FIR0_FLOAT
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%endif
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INIT_XMM sse2
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LFE_FIR0_FLOAT
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%if HAVE_AVX_EXTERNAL
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INIT_XMM avx
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LFE_FIR0_FLOAT
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%endif
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%if HAVE_FMA3_EXTERNAL
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INIT_XMM fma3
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LFE_FIR0_FLOAT
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%endif
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%macro LFE_FIR1_FLOAT 0
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cglobal lfe_fir1_float, 4, 6, 10, samples, lfe, coeff, nblocks, cnt1, cnt2
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shr nblocksd, 2
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sub lfeq, 3*sizeof_float
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mov cnt1d, 64*sizeof_float
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mov cnt2d, 64*sizeof_float-16
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lea coeffq, [coeffq+cnt1q*4]
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add samplesq, cnt1q
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neg cnt1q
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.loop:
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%if cpuflag(avx)
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cvtdq2ps m4, [lfeq]
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shufps m5, m4, m4, q0123
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%elif cpuflag(sse2)
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movu m4, [lfeq]
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cvtdq2ps m4, m4
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pshufd m5, m4, q0123
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%endif
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.inner_loop:
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movaps m6, [coeffq+cnt1q*4 ]
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movaps m7, [coeffq+cnt1q*4+16]
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mulps m0, m5, m6
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mulps m1, m5, m7
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%if ARCH_X86_64
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movaps m8, [coeffq+cnt1q*4+32]
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movaps m9, [coeffq+cnt1q*4+48]
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mulps m2, m5, m8
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mulps m3, m5, m9
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%else
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mulps m2, m5, [coeffq+cnt1q*4+32]
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mulps m3, m5, [coeffq+cnt1q*4+48]
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%endif
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haddps m0, m1
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haddps m2, m3
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haddps m0, m2
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movaps [samplesq+cnt1q], m0
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mulps m6, m4
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mulps m7, m4
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%if ARCH_X86_64
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mulps m8, m4
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mulps m9, m4
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haddps m6, m7
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haddps m8, m9
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haddps m6, m8
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%else
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mulps m2, m4, [coeffq+cnt1q*4+32]
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mulps m3, m4, [coeffq+cnt1q*4+48]
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haddps m6, m7
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haddps m2, m3
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haddps m6, m2
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%endif
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movaps [samplesq+cnt2q], m6
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sub cnt2d, 16
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add cnt1q, 16
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jl .inner_loop
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add lfeq, sizeof_float
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add samplesq, 128*sizeof_float
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mov cnt1q, -64*sizeof_float
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mov cnt2d, 64*sizeof_float-16
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sub nblocksd, 1
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jg .loop
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RET
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%endmacro
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INIT_XMM sse3
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LFE_FIR1_FLOAT
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%if HAVE_AVX_EXTERNAL
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INIT_XMM avx
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LFE_FIR1_FLOAT
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%endif
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