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/*
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* Copyright (c) 2016 Clément Bœsch <clement stupeflix.com>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/aarch64/asm.S"
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function ff_yuv2planeX_8_neon, export=1
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// x0 - const int16_t *filter,
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// x1 - int filterSize,
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// x2 - const int16_t **src,
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// x3 - uint8_t *dest,
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// w4 - int dstW,
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// x5 - const uint8_t *dither,
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// w6 - int offset
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ld1 {v0.8b}, [x5] // load 8x8-bit dither
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and w6, w6, #7
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cbz w6, 1f // check if offsetting present
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ext v0.8b, v0.8b, v0.8b, #3 // honor offsetting which can be 0 or 3 only
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1: uxtl v0.8h, v0.8b // extend dither to 16-bit
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ushll v1.4s, v0.4h, #12 // extend dither to 32-bit with left shift by 12 (part 1)
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ushll2 v2.4s, v0.8h, #12 // extend dither to 32-bit with left shift by 12 (part 2)
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cmp w1, #8 // if filterSize == 8, branch to specialized version
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b.eq 6f
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cmp w1, #4 // if filterSize == 4, branch to specialized version
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b.eq 8f
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cmp w1, #2 // if filterSize == 2, branch to specialized version
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b.eq 10f
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// The filter size does not match of the of specialized implementations. It is either even or odd. If it is even
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// then use the first section below.
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mov x7, #0 // i = 0
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tbnz w1, #0, 4f // if filterSize % 2 != 0 branch to specialized version
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// fs % 2 == 0
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2: mov v3.16b, v1.16b // initialize accumulator part 1 with dithering value
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mov v4.16b, v2.16b // initialize accumulator part 2 with dithering value
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mov w8, w1 // tmpfilterSize = filterSize
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mov x9, x2 // srcp = src
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mov x10, x0 // filterp = filter
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3: ldp x11, x12, [x9], #16 // get 2 pointers: src[j] and src[j+1]
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ldr s7, [x10], #4 // read 2x16-bit coeff X and Y at filter[j] and filter[j+1]
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add x11, x11, x7, lsl #1 // &src[j ][i]
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add x12, x12, x7, lsl #1 // &src[j+1][i]
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ld1 {v5.8h}, [x11] // read 8x16-bit @ src[j ][i + {0..7}]: A,B,C,D,E,F,G,H
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ld1 {v6.8h}, [x12] // read 8x16-bit @ src[j+1][i + {0..7}]: I,J,K,L,M,N,O,P
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smlal v3.4s, v5.4h, v7.h[0] // val0 += {A,B,C,D} * X
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smlal2 v4.4s, v5.8h, v7.h[0] // val1 += {E,F,G,H} * X
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smlal v3.4s, v6.4h, v7.h[1] // val0 += {I,J,K,L} * Y
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smlal2 v4.4s, v6.8h, v7.h[1] // val1 += {M,N,O,P} * Y
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subs w8, w8, #2 // tmpfilterSize -= 2
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b.gt 3b // loop until filterSize consumed
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sqshrun v3.4h, v3.4s, #16 // clip16(val0>>16)
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sqshrun2 v3.8h, v4.4s, #16 // clip16(val1>>16)
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uqshrn v3.8b, v3.8h, #3 // clip8(val>>19)
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st1 {v3.8b}, [x3], #8 // write to destination
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subs w4, w4, #8 // dstW -= 8
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add x7, x7, #8 // i += 8
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b.gt 2b // loop until width consumed
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ret
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// If filter size is odd (most likely == 1), then use this section.
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// fs % 2 != 0
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4: mov v3.16b, v1.16b // initialize accumulator part 1 with dithering value
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mov v4.16b, v2.16b // initialize accumulator part 2 with dithering value
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mov w8, w1 // tmpfilterSize = filterSize
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mov x9, x2 // srcp = src
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mov x10, x0 // filterp = filter
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5: ldr x11, [x9], #8 // get 1 pointer: src[j]
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ldr h6, [x10], #2 // read 1 16 bit coeff X at filter[j]
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add x11, x11, x7, lsl #1 // &src[j ][i]
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ld1 {v5.8h}, [x11] // read 8x16-bit @ src[j ][i + {0..7}]: A,B,C,D,E,F,G,H
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smlal v3.4s, v5.4h, v6.h[0] // val0 += {A,B,C,D} * X
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smlal2 v4.4s, v5.8h, v6.h[0] // val1 += {E,F,G,H} * X
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subs w8, w8, #1 // tmpfilterSize -= 2
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b.gt 5b // loop until filterSize consumed
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sqshrun v3.4h, v3.4s, #16 // clip16(val0>>16)
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sqshrun2 v3.8h, v4.4s, #16 // clip16(val1>>16)
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uqshrn v3.8b, v3.8h, #3 // clip8(val>>19)
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st1 {v3.8b}, [x3], #8 // write to destination
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subs w4, w4, #8 // dstW -= 8
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add x7, x7, #8 // i += 8
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b.gt 4b // loop until width consumed
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ret
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6: // fs=8
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ldp x5, x6, [x2] // load 2 pointers: src[j ] and src[j+1]
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ldp x7, x9, [x2, #16] // load 2 pointers: src[j+2] and src[j+3]
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ldp x10, x11, [x2, #32] // load 2 pointers: src[j+4] and src[j+5]
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ldp x12, x13, [x2, #48] // load 2 pointers: src[j+6] and src[j+7]
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// load 8x16-bit values for filter[j], where j=0..7
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ld1 {v6.8h}, [x0]
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7:
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mov v3.16b, v1.16b // initialize accumulator part 1 with dithering value
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mov v4.16b, v2.16b // initialize accumulator part 2 with dithering value
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ld1 {v24.8h}, [x5], #16 // load 8x16-bit values for src[j + 0][i + {0..7}]
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ld1 {v25.8h}, [x6], #16 // load 8x16-bit values for src[j + 1][i + {0..7}]
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ld1 {v26.8h}, [x7], #16 // load 8x16-bit values for src[j + 2][i + {0..7}]
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ld1 {v27.8h}, [x9], #16 // load 8x16-bit values for src[j + 3][i + {0..7}]
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ld1 {v28.8h}, [x10], #16 // load 8x16-bit values for src[j + 4][i + {0..7}]
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ld1 {v29.8h}, [x11], #16 // load 8x16-bit values for src[j + 5][i + {0..7}]
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ld1 {v30.8h}, [x12], #16 // load 8x16-bit values for src[j + 6][i + {0..7}]
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ld1 {v31.8h}, [x13], #16 // load 8x16-bit values for src[j + 7][i + {0..7}]
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smlal v3.4s, v24.4h, v6.h[0] // val0 += src[0][i + {0..3}] * filter[0]
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smlal2 v4.4s, v24.8h, v6.h[0] // val1 += src[0][i + {4..7}] * filter[0]
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smlal v3.4s, v25.4h, v6.h[1] // val0 += src[1][i + {0..3}] * filter[1]
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smlal2 v4.4s, v25.8h, v6.h[1] // val1 += src[1][i + {4..7}] * filter[1]
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smlal v3.4s, v26.4h, v6.h[2] // val0 += src[2][i + {0..3}] * filter[2]
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smlal2 v4.4s, v26.8h, v6.h[2] // val1 += src[2][i + {4..7}] * filter[2]
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smlal v3.4s, v27.4h, v6.h[3] // val0 += src[3][i + {0..3}] * filter[3]
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smlal2 v4.4s, v27.8h, v6.h[3] // val1 += src[3][i + {4..7}] * filter[3]
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smlal v3.4s, v28.4h, v6.h[4] // val0 += src[4][i + {0..3}] * filter[4]
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smlal2 v4.4s, v28.8h, v6.h[4] // val1 += src[4][i + {4..7}] * filter[4]
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smlal v3.4s, v29.4h, v6.h[5] // val0 += src[5][i + {0..3}] * filter[5]
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smlal2 v4.4s, v29.8h, v6.h[5] // val1 += src[5][i + {4..7}] * filter[5]
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smlal v3.4s, v30.4h, v6.h[6] // val0 += src[6][i + {0..3}] * filter[6]
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smlal2 v4.4s, v30.8h, v6.h[6] // val1 += src[6][i + {4..7}] * filter[6]
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smlal v3.4s, v31.4h, v6.h[7] // val0 += src[7][i + {0..3}] * filter[7]
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smlal2 v4.4s, v31.8h, v6.h[7] // val1 += src[7][i + {4..7}] * filter[7]
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sqshrun v3.4h, v3.4s, #16 // clip16(val0>>16)
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sqshrun2 v3.8h, v4.4s, #16 // clip16(val1>>16)
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uqshrn v3.8b, v3.8h, #3 // clip8(val>>19)
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subs w4, w4, #8 // dstW -= 8
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st1 {v3.8b}, [x3], #8 // write to destination
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b.gt 7b // loop until width consumed
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ret
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8: // fs=4
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ldp x5, x6, [x2] // load 2 pointers: src[j ] and src[j+1]
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ldp x7, x9, [x2, #16] // load 2 pointers: src[j+2] and src[j+3]
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// load 4x16-bit values for filter[j], where j=0..3 and replicated across lanes
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ld1 {v6.4h}, [x0]
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9:
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mov v3.16b, v1.16b // initialize accumulator part 1 with dithering value
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mov v4.16b, v2.16b // initialize accumulator part 2 with dithering value
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ld1 {v24.8h}, [x5], #16 // load 8x16-bit values for src[j + 0][i + {0..7}]
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ld1 {v25.8h}, [x6], #16 // load 8x16-bit values for src[j + 1][i + {0..7}]
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ld1 {v26.8h}, [x7], #16 // load 8x16-bit values for src[j + 2][i + {0..7}]
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ld1 {v27.8h}, [x9], #16 // load 8x16-bit values for src[j + 3][i + {0..7}]
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smlal v3.4s, v24.4h, v6.h[0] // val0 += src[0][i + {0..3}] * filter[0]
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smlal2 v4.4s, v24.8h, v6.h[0] // val1 += src[0][i + {4..7}] * filter[0]
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smlal v3.4s, v25.4h, v6.h[1] // val0 += src[1][i + {0..3}] * filter[1]
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smlal2 v4.4s, v25.8h, v6.h[1] // val1 += src[1][i + {4..7}] * filter[1]
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smlal v3.4s, v26.4h, v6.h[2] // val0 += src[2][i + {0..3}] * filter[2]
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smlal2 v4.4s, v26.8h, v6.h[2] // val1 += src[2][i + {4..7}] * filter[2]
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smlal v3.4s, v27.4h, v6.h[3] // val0 += src[3][i + {0..3}] * filter[3]
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smlal2 v4.4s, v27.8h, v6.h[3] // val1 += src[3][i + {4..7}] * filter[3]
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sqshrun v3.4h, v3.4s, #16 // clip16(val0>>16)
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sqshrun2 v3.8h, v4.4s, #16 // clip16(val1>>16)
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uqshrn v3.8b, v3.8h, #3 // clip8(val>>19)
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st1 {v3.8b}, [x3], #8 // write to destination
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subs w4, w4, #8 // dstW -= 8
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b.gt 9b // loop until width consumed
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ret
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10: // fs=2
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ldp x5, x6, [x2] // load 2 pointers: src[j ] and src[j+1]
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// load 2x16-bit values for filter[j], where j=0..1 and replicated across lanes
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ldr s6, [x0]
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11:
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mov v3.16b, v1.16b // initialize accumulator part 1 with dithering value
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mov v4.16b, v2.16b // initialize accumulator part 2 with dithering value
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ld1 {v24.8h}, [x5], #16 // load 8x16-bit values for src[j + 0][i + {0..7}]
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ld1 {v25.8h}, [x6], #16 // load 8x16-bit values for src[j + 1][i + {0..7}]
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smlal v3.4s, v24.4h, v6.h[0] // val0 += src[0][i + {0..3}] * filter[0]
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smlal2 v4.4s, v24.8h, v6.h[0] // val1 += src[0][i + {4..7}] * filter[0]
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smlal v3.4s, v25.4h, v6.h[1] // val0 += src[1][i + {0..3}] * filter[1]
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smlal2 v4.4s, v25.8h, v6.h[1] // val1 += src[1][i + {4..7}] * filter[1]
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sqshrun v3.4h, v3.4s, #16 // clip16(val0>>16)
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sqshrun2 v3.8h, v4.4s, #16 // clip16(val1>>16)
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uqshrn v3.8b, v3.8h, #3 // clip8(val>>19)
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st1 {v3.8b}, [x3], #8 // write to destination
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subs w4, w4, #8 // dstW -= 8
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b.gt 11b // loop until width consumed
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ret
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endfunc
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function ff_yuv2plane1_8_neon, export=1
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// x0 - const int16_t *src,
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// x1 - uint8_t *dest,
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// w2 - int dstW,
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// x3 - const uint8_t *dither,
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// w4 - int offset
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ld1 {v0.8b}, [x3] // load 8x8-bit dither
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and w4, w4, #7
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cbz w4, 1f // check if offsetting present
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ext v0.8b, v0.8b, v0.8b, #3 // honor offsetting which can be 0 or 3 only
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1: uxtl v0.8h, v0.8b // extend dither to 32-bit
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uxtl v1.4s, v0.4h
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uxtl2 v2.4s, v0.8h
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2:
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ld1 {v3.8h}, [x0], #16 // read 8x16-bit @ src[j ][i + {0..7}]: A,B,C,D,E,F,G,H
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sxtl v4.4s, v3.4h
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sxtl2 v5.4s, v3.8h
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add v4.4s, v4.4s, v1.4s
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add v5.4s, v5.4s, v2.4s
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sqshrun v4.4h, v4.4s, #6
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sqshrun2 v4.8h, v5.4s, #6
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uqshrn v3.8b, v4.8h, #1 // clip8(val>>7)
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subs w2, w2, #8 // dstW -= 8
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st1 {v3.8b}, [x1], #8 // write to destination
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b.gt 2b // loop until width consumed
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ret
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endfunc
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