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/*
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* Loongson SIMD optimized pixblockdsp
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*
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* Copyright (c) 2015 Loongson Technology Corporation Limited
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* Copyright (c) 2015 Zhou Xiaoyong <zhouxiaoyong@loongson.cn>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "pixblockdsp_mips.h"
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#include "libavutil/mips/asmdefs.h"
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#include "libavutil/mips/mmiutils.h"
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void ff_get_pixels_8_mmi(int16_t *av_restrict block, const uint8_t *pixels,
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ptrdiff_t stride)
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{
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double ftmp[7];
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DECLARE_VAR_ALL64;
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DECLARE_VAR_ADDRT;
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__asm__ volatile (
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libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
4 years ago
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"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
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MMI_LDC1(%[ftmp1], %[pixels], 0x00)
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MMI_LDXC1(%[ftmp2], %[pixels], %[stride], 0x00)
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"punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
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"punpckhbh %[ftmp4], %[ftmp1], %[ftmp0] \n\t"
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"punpcklbh %[ftmp5], %[ftmp2], %[ftmp0] \n\t"
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"punpckhbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t"
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MMI_SDC1(%[ftmp3], %[block], 0x00)
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MMI_SDC1(%[ftmp4], %[block], 0x08)
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MMI_SDC1(%[ftmp5], %[block], 0x10)
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MMI_SDC1(%[ftmp6], %[block], 0x18)
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PTR_ADDU "%[pixels], %[pixels], %[stride_x2] \n\t"
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MMI_LDC1(%[ftmp1], %[pixels], 0x00)
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MMI_LDXC1(%[ftmp2], %[pixels], %[stride], 0x00)
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"punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
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"punpckhbh %[ftmp4], %[ftmp1], %[ftmp0] \n\t"
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"punpcklbh %[ftmp5], %[ftmp2], %[ftmp0] \n\t"
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"punpckhbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t"
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MMI_SDC1(%[ftmp3], %[block], 0x20)
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MMI_SDC1(%[ftmp4], %[block], 0x28)
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MMI_SDC1(%[ftmp5], %[block], 0x30)
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MMI_SDC1(%[ftmp6], %[block], 0x38)
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PTR_ADDU "%[pixels], %[pixels], %[stride_x2] \n\t"
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MMI_LDC1(%[ftmp1], %[pixels], 0x00)
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MMI_LDXC1(%[ftmp2], %[pixels], %[stride], 0x00)
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"punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
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"punpckhbh %[ftmp4], %[ftmp1], %[ftmp0] \n\t"
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"punpcklbh %[ftmp5], %[ftmp2], %[ftmp0] \n\t"
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"punpckhbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t"
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MMI_SDC1(%[ftmp3], %[block], 0x40)
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MMI_SDC1(%[ftmp4], %[block], 0x48)
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MMI_SDC1(%[ftmp5], %[block], 0x50)
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MMI_SDC1(%[ftmp6], %[block], 0x58)
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PTR_ADDU "%[pixels], %[pixels], %[stride_x2] \n\t"
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MMI_LDC1(%[ftmp1], %[pixels], 0x00)
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MMI_LDXC1(%[ftmp2], %[pixels], %[stride], 0x00)
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"punpcklbh %[ftmp3], %[ftmp1], %[ftmp0] \n\t"
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"punpckhbh %[ftmp4], %[ftmp1], %[ftmp0] \n\t"
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"punpcklbh %[ftmp5], %[ftmp2], %[ftmp0] \n\t"
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"punpckhbh %[ftmp6], %[ftmp2], %[ftmp0] \n\t"
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MMI_SDC1(%[ftmp3], %[block], 0x60)
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MMI_SDC1(%[ftmp4], %[block], 0x68)
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MMI_SDC1(%[ftmp5], %[block], 0x70)
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MMI_SDC1(%[ftmp6], %[block], 0x78)
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: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
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[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
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[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
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[ftmp6]"=&f"(ftmp[6]),
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RESTRICT_ASM_ALL64
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RESTRICT_ASM_ADDRT
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[pixels]"+&r"(pixels)
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: [block]"r"((mips_reg)block), [stride]"r"((mips_reg)stride),
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[stride_x2]"r"((mips_reg)(stride<<1))
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: "memory"
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);
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}
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void ff_diff_pixels_mmi(int16_t *av_restrict block, const uint8_t *src1,
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const uint8_t *src2, ptrdiff_t stride)
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{
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double ftmp[5];
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mips_reg tmp[1];
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DECLARE_VAR_ALL64;
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__asm__ volatile (
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"li %[tmp0], 0x08 \n\t"
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libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
4 years ago
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"pxor %[ftmp4], %[ftmp4], %[ftmp4] \n\t"
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"1: \n\t"
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MMI_LDC1(%[ftmp0], %[src1], 0x00)
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libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
4 years ago
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"por %[ftmp1], %[ftmp0], %[ftmp0] \n\t"
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MMI_LDC1(%[ftmp2], %[src2], 0x00)
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libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
4 years ago
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"por %[ftmp3], %[ftmp2], %[ftmp2] \n\t"
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"punpcklbh %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
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"punpckhbh %[ftmp1], %[ftmp1], %[ftmp4] \n\t"
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"punpcklbh %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
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"punpckhbh %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
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"psubh %[ftmp0], %[ftmp0], %[ftmp2] \n\t"
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"psubh %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
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MMI_SDC1(%[ftmp0], %[block], 0x00)
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MMI_SDC1(%[ftmp1], %[block], 0x08)
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PTR_ADDI "%[tmp0], %[tmp0], -0x01 \n\t"
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PTR_ADDIU "%[block], %[block], 0x10 \n\t"
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PTR_ADDU "%[src1], %[src1], %[stride] \n\t"
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PTR_ADDU "%[src2], %[src2], %[stride] \n\t"
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"bgtz %[tmp0], 1b \n\t"
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: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
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[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
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[ftmp4]"=&f"(ftmp[4]),
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[tmp0]"=&r"(tmp[0]),
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RESTRICT_ASM_ALL64
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[block]"+&r"(block), [src1]"+&r"(src1),
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[src2]"+&r"(src2)
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: [stride]"r"((mips_reg)stride)
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: "memory"
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);
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}
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