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/*
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* ARM NEON optimised DSP functions
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* Copyright (c) 2008 Mans Rullgard <mans@mansr.com>
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*
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* This file is part of Libav.
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*
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* Libav is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* Libav is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with Libav; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/arm/asm.S"
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function ff_clear_block_neon, export=1
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vmov.i16 q0, #0
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.rept 8
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vst1.16 {q0}, [r0,:128]!
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.endr
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bx lr
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endfunc
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function ff_clear_blocks_neon, export=1
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vmov.i16 q0, #0
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.rept 8*6
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vst1.16 {q0}, [r0,:128]!
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.endr
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bx lr
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endfunc
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function ff_put_pixels_clamped_neon, export=1
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vld1.16 {d16-d19}, [r0,:128]!
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vqmovun.s16 d0, q8
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vld1.16 {d20-d23}, [r0,:128]!
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vqmovun.s16 d1, q9
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vld1.16 {d24-d27}, [r0,:128]!
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vqmovun.s16 d2, q10
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vld1.16 {d28-d31}, [r0,:128]!
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vqmovun.s16 d3, q11
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vst1.8 {d0}, [r1,:64], r2
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vqmovun.s16 d4, q12
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vst1.8 {d1}, [r1,:64], r2
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vqmovun.s16 d5, q13
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vst1.8 {d2}, [r1,:64], r2
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vqmovun.s16 d6, q14
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vst1.8 {d3}, [r1,:64], r2
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vqmovun.s16 d7, q15
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vst1.8 {d4}, [r1,:64], r2
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vst1.8 {d5}, [r1,:64], r2
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vst1.8 {d6}, [r1,:64], r2
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vst1.8 {d7}, [r1,:64], r2
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bx lr
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endfunc
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function ff_put_signed_pixels_clamped_neon, export=1
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vmov.u8 d31, #128
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vld1.16 {d16-d17}, [r0,:128]!
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vqmovn.s16 d0, q8
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vld1.16 {d18-d19}, [r0,:128]!
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vqmovn.s16 d1, q9
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vld1.16 {d16-d17}, [r0,:128]!
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vqmovn.s16 d2, q8
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vld1.16 {d18-d19}, [r0,:128]!
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vadd.u8 d0, d0, d31
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vld1.16 {d20-d21}, [r0,:128]!
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vadd.u8 d1, d1, d31
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vld1.16 {d22-d23}, [r0,:128]!
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vadd.u8 d2, d2, d31
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vst1.8 {d0}, [r1,:64], r2
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vqmovn.s16 d3, q9
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vst1.8 {d1}, [r1,:64], r2
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vqmovn.s16 d4, q10
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vst1.8 {d2}, [r1,:64], r2
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vqmovn.s16 d5, q11
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vld1.16 {d24-d25}, [r0,:128]!
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vadd.u8 d3, d3, d31
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vld1.16 {d26-d27}, [r0,:128]!
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vadd.u8 d4, d4, d31
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vadd.u8 d5, d5, d31
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vst1.8 {d3}, [r1,:64], r2
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vqmovn.s16 d6, q12
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vst1.8 {d4}, [r1,:64], r2
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vqmovn.s16 d7, q13
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vst1.8 {d5}, [r1,:64], r2
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vadd.u8 d6, d6, d31
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vadd.u8 d7, d7, d31
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vst1.8 {d6}, [r1,:64], r2
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vst1.8 {d7}, [r1,:64], r2
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bx lr
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endfunc
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function ff_add_pixels_clamped_neon, export=1
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mov r3, r1
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vld1.8 {d16}, [r1,:64], r2
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vld1.16 {d0-d1}, [r0,:128]!
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vaddw.u8 q0, q0, d16
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vld1.8 {d17}, [r1,:64], r2
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vld1.16 {d2-d3}, [r0,:128]!
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vqmovun.s16 d0, q0
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vld1.8 {d18}, [r1,:64], r2
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vaddw.u8 q1, q1, d17
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vld1.16 {d4-d5}, [r0,:128]!
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vaddw.u8 q2, q2, d18
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vst1.8 {d0}, [r3,:64], r2
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vqmovun.s16 d2, q1
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vld1.8 {d19}, [r1,:64], r2
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vld1.16 {d6-d7}, [r0,:128]!
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vaddw.u8 q3, q3, d19
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vqmovun.s16 d4, q2
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vst1.8 {d2}, [r3,:64], r2
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vld1.8 {d16}, [r1,:64], r2
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vqmovun.s16 d6, q3
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vld1.16 {d0-d1}, [r0,:128]!
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vaddw.u8 q0, q0, d16
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vst1.8 {d4}, [r3,:64], r2
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vld1.8 {d17}, [r1,:64], r2
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vld1.16 {d2-d3}, [r0,:128]!
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vaddw.u8 q1, q1, d17
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vst1.8 {d6}, [r3,:64], r2
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vqmovun.s16 d0, q0
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vld1.8 {d18}, [r1,:64], r2
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vld1.16 {d4-d5}, [r0,:128]!
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vaddw.u8 q2, q2, d18
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vst1.8 {d0}, [r3,:64], r2
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vqmovun.s16 d2, q1
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vld1.8 {d19}, [r1,:64], r2
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vqmovun.s16 d4, q2
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vld1.16 {d6-d7}, [r0,:128]!
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vaddw.u8 q3, q3, d19
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vst1.8 {d2}, [r3,:64], r2
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vqmovun.s16 d6, q3
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vst1.8 {d4}, [r3,:64], r2
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vst1.8 {d6}, [r3,:64], r2
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bx lr
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endfunc
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function ff_vector_clipf_neon, export=1
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VFP vdup.32 q1, d0[1]
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VFP vdup.32 q0, d0[0]
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NOVFP vdup.32 q0, r2
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NOVFP vdup.32 q1, r3
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NOVFP ldr r2, [sp]
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vld1.f32 {q2},[r1,:128]!
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vmin.f32 q10, q2, q1
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vld1.f32 {q3},[r1,:128]!
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vmin.f32 q11, q3, q1
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1: vmax.f32 q8, q10, q0
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vmax.f32 q9, q11, q0
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subs r2, r2, #8
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beq 2f
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vld1.f32 {q2},[r1,:128]!
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vmin.f32 q10, q2, q1
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vld1.f32 {q3},[r1,:128]!
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vmin.f32 q11, q3, q1
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vst1.f32 {q8},[r0,:128]!
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vst1.f32 {q9},[r0,:128]!
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b 1b
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2: vst1.f32 {q8},[r0,:128]!
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vst1.f32 {q9},[r0,:128]!
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bx lr
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endfunc
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function ff_vector_clip_int32_neon, export=1
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vdup.32 q0, r2
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vdup.32 q1, r3
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ldr r2, [sp]
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1:
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vld1.32 {q2-q3}, [r1,:128]!
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vmin.s32 q2, q2, q1
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vmin.s32 q3, q3, q1
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vmax.s32 q2, q2, q0
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vmax.s32 q3, q3, q0
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vst1.32 {q2-q3}, [r0,:128]!
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subs r2, r2, #8
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bgt 1b
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bx lr
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endfunc
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